tlb.cc (7733:08d6a773d1b6) | tlb.cc (7734:85a8198aa2ff) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 138 unchanged lines hidden (view full) --- 147 table[size-1].pfn << table[size-1].N, table[size-1].size, 148 table[size-1].ap); 149 150 //inserting to MRU position and evicting the LRU one 151 152 for(int i = size-1; i > 0; i--) 153 table[i] = table[i-1]; 154 table[0] = entry; | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 138 unchanged lines hidden (view full) --- 147 table[size-1].pfn << table[size-1].N, table[size-1].size, 148 table[size-1].ap); 149 150 //inserting to MRU position and evicting the LRU one 151 152 for(int i = size-1; i > 0; i--) 153 table[i] = table[i-1]; 154 table[0] = entry; |
155 156 inserts++; |
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155} 156 157void 158TLB::printTlb() 159{ 160 int x = 0; 161 TlbEntry *te; 162 DPRINTF(TLB, "Current TLB contents:\n"); --- 10 unchanged lines hidden (view full) --- 173void 174TLB::flushAll() 175{ 176 DPRINTF(TLB, "Flushing all TLB entries\n"); 177 int x = 0; 178 TlbEntry *te; 179 while (x < size) { 180 te = &table[x]; | 157} 158 159void 160TLB::printTlb() 161{ 162 int x = 0; 163 TlbEntry *te; 164 DPRINTF(TLB, "Current TLB contents:\n"); --- 10 unchanged lines hidden (view full) --- 175void 176TLB::flushAll() 177{ 178 DPRINTF(TLB, "Flushing all TLB entries\n"); 179 int x = 0; 180 TlbEntry *te; 181 while (x < size) { 182 te = &table[x]; |
181 if (te->valid) | 183 if (te->valid) { |
182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); | 184 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 185 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); |
186 flushedEntries++; 187 } |
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184 x++; 185 } 186 187 memset(table, 0, sizeof(TlbEntry[size])); | 188 x++; 189 } 190 191 memset(table, 0, sizeof(TlbEntry[size])); |
192 193 flushTlb++; |
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188} 189 190 191void 192TLB::flushMvaAsid(Addr mva, uint64_t asn) 193{ 194 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 195 TlbEntry *te; 196 197 te = lookup(mva, asn); 198 while (te != NULL) { 199 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 200 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 201 te->valid = false; | 194} 195 196 197void 198TLB::flushMvaAsid(Addr mva, uint64_t asn) 199{ 200 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 201 TlbEntry *te; 202 203 te = lookup(mva, asn); 204 while (te != NULL) { 205 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 206 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 207 te->valid = false; |
208 flushedEntries++; |
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202 te = lookup(mva,asn); 203 } | 209 te = lookup(mva,asn); 210 } |
211 flushTlbMvaAsid++; |
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204} 205 206void 207TLB::flushAsid(uint64_t asn) 208{ 209 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 210 211 int x = 0; 212 TlbEntry *te; 213 214 while (x < size) { 215 te = &table[x]; 216 if (te->asid == asn) { 217 te->valid = false; 218 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 219 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); | 212} 213 214void 215TLB::flushAsid(uint64_t asn) 216{ 217 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 218 219 int x = 0; 220 TlbEntry *te; 221 222 while (x < size) { 223 te = &table[x]; 224 if (te->asid == asn) { 225 te->valid = false; 226 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 227 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); |
228 flushedEntries++; |
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220 } 221 x++; 222 } | 229 } 230 x++; 231 } |
232 flushTlbAsid++; |
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223} 224 225void 226TLB::flushMva(Addr mva) 227{ 228 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 229 230 int x = 0; 231 TlbEntry *te; 232 233 while (x < size) { 234 te = &table[x]; 235 Addr v = te->vpn << te->N; 236 if (mva >= v && mva < v + te->size) { 237 te->valid = false; 238 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 239 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); | 233} 234 235void 236TLB::flushMva(Addr mva) 237{ 238 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 239 240 int x = 0; 241 TlbEntry *te; 242 243 while (x < size) { 244 te = &table[x]; 245 Addr v = te->vpn << te->N; 246 if (mva >= v && mva < v + te->size) { 247 te->valid = false; 248 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 249 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); |
250 flushedEntries++; |
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240 } 241 x++; 242 } | 251 } 252 x++; 253 } |
254 flushTlbMva++; |
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243} 244 245void 246TLB::serialize(ostream &os) 247{ 248 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 249 250 SERIALIZE_SCALAR(_attr); --- 12 unchanged lines hidden (view full) --- 263 for(int i = 0; i < size; i++){ 264 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 265 } 266} 267 268void 269TLB::regStats() 270{ | 255} 256 257void 258TLB::serialize(ostream &os) 259{ 260 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 261 262 SERIALIZE_SCALAR(_attr); --- 12 unchanged lines hidden (view full) --- 275 for(int i = 0; i < size; i++){ 276 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 277 } 278} 279 280void 281TLB::regStats() 282{ |
271 read_hits | 283 instHits 284 .name(name() + ".inst_hits") 285 .desc("ITB inst hits") 286 ; 287 288 instMisses 289 .name(name() + ".inst_misses") 290 .desc("ITB inst misses") 291 ; 292 293 instAccesses 294 .name(name() + ".inst_accesses") 295 .desc("ITB inst accesses") 296 ; 297 298 readHits |
272 .name(name() + ".read_hits") 273 .desc("DTB read hits") 274 ; 275 | 299 .name(name() + ".read_hits") 300 .desc("DTB read hits") 301 ; 302 |
276 read_misses | 303 readMisses |
277 .name(name() + ".read_misses") 278 .desc("DTB read misses") 279 ; 280 | 304 .name(name() + ".read_misses") 305 .desc("DTB read misses") 306 ; 307 |
281 282 read_accesses | 308 readAccesses |
283 .name(name() + ".read_accesses") 284 .desc("DTB read accesses") 285 ; 286 | 309 .name(name() + ".read_accesses") 310 .desc("DTB read accesses") 311 ; 312 |
287 write_hits | 313 writeHits |
288 .name(name() + ".write_hits") 289 .desc("DTB write hits") 290 ; 291 | 314 .name(name() + ".write_hits") 315 .desc("DTB write hits") 316 ; 317 |
292 write_misses | 318 writeMisses |
293 .name(name() + ".write_misses") 294 .desc("DTB write misses") 295 ; 296 | 319 .name(name() + ".write_misses") 320 .desc("DTB write misses") 321 ; 322 |
297 298 write_accesses | 323 writeAccesses |
299 .name(name() + ".write_accesses") 300 .desc("DTB write accesses") 301 ; 302 303 hits 304 .name(name() + ".hits") 305 .desc("DTB hits") 306 ; 307 308 misses 309 .name(name() + ".misses") 310 .desc("DTB misses") 311 ; 312 313 accesses 314 .name(name() + ".accesses") 315 .desc("DTB accesses") 316 ; 317 | 324 .name(name() + ".write_accesses") 325 .desc("DTB write accesses") 326 ; 327 328 hits 329 .name(name() + ".hits") 330 .desc("DTB hits") 331 ; 332 333 misses 334 .name(name() + ".misses") 335 .desc("DTB misses") 336 ; 337 338 accesses 339 .name(name() + ".accesses") 340 .desc("DTB accesses") 341 ; 342 |
318 hits = read_hits + write_hits; 319 misses = read_misses + write_misses; 320 accesses = read_accesses + write_accesses; | 343 flushTlb 344 .name(name() + ".flush_tlb") 345 .desc("Number of times complete TLB was flushed") 346 ; 347 348 flushTlbMva 349 .name(name() + ".flush_tlb_mva") 350 .desc("Number of times TLB was flushed by MVA") 351 ; 352 353 flushTlbMvaAsid 354 .name(name() + ".flush_tlb_mva_asid") 355 .desc("Number of times TLB was flushed by MVA & ASID") 356 ; 357 358 flushTlbAsid 359 .name(name() + ".flush_tlb_asid") 360 .desc("Number of times TLB was flushed by ASID") 361 ; 362 363 flushedEntries 364 .name(name() + ".flush_entries") 365 .desc("Number of entries that have been flushed from TLB") 366 ; 367 368 alignFaults 369 .name(name() + ".align_faults") 370 .desc("Number of TLB faults due to alignment restrictions") 371 ; 372 373 prefetchFaults 374 .name(name() + ".prefetch_faults") 375 .desc("Number of TLB faults due to prefetch") 376 ; 377 378 domainFaults 379 .name(name() + ".domain_faults") 380 .desc("Number of TLB faults due to domain restrictions") 381 ; 382 383 permsFaults 384 .name(name() + ".perms_faults") 385 .desc("Number of TLB faults due to permissions restrictions") 386 ; 387 388 instAccesses = instHits + instMisses; 389 readAccesses = readHits + readMisses; 390 writeAccesses = writeHits + writeMisses; 391 hits = readHits + writeHits + instHits; 392 misses = readMisses + writeMisses + instMisses; 393 accesses = readAccesses + writeAccesses + instAccesses; |
321} 322 323#if !FULL_SYSTEM 324Fault 325TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 326 Translation *translation, bool &delay, bool timing) 327{ 328 // XXX Cache misc registers and have miscreg write function inv cache --- 66 unchanged lines hidden (view full) --- 395 if ((req->isInstFetch() && (!sctlr.i)) || 396 ((!req->isInstFetch()) && (!sctlr.c))){ 397 req->setFlags(Request::UNCACHEABLE); 398 } 399 if (!is_fetch) { 400 assert(flags & MustBeOne); 401 if (sctlr.a || !(flags & AllowUnaligned)) { 402 if (vaddr & flags & AlignmentMask) { | 394} 395 396#if !FULL_SYSTEM 397Fault 398TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 399 Translation *translation, bool &delay, bool timing) 400{ 401 // XXX Cache misc registers and have miscreg write function inv cache --- 66 unchanged lines hidden (view full) --- 468 if ((req->isInstFetch() && (!sctlr.i)) || 469 ((!req->isInstFetch()) && (!sctlr.c))){ 470 req->setFlags(Request::UNCACHEABLE); 471 } 472 if (!is_fetch) { 473 assert(flags & MustBeOne); 474 if (sctlr.a || !(flags & AllowUnaligned)) { 475 if (vaddr & flags & AlignmentMask) { |
476 alignFaults++; |
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403 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 404 } 405 } 406 } 407 408 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 409 Fault fault; 410 --- 25 unchanged lines hidden (view full) --- 436 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 437 // Translation enabled 438 439 TlbEntry *te = lookup(vaddr, context_id); 440 if (te == NULL) { 441 if (req->isPrefetch()){ 442 //if the request is a prefetch don't attempt to fill the TLB 443 //or go any further with the memory access | 477 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 478 } 479 } 480 } 481 482 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 483 Fault fault; 484 --- 25 unchanged lines hidden (view full) --- 510 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 511 // Translation enabled 512 513 TlbEntry *te = lookup(vaddr, context_id); 514 if (te == NULL) { 515 if (req->isPrefetch()){ 516 //if the request is a prefetch don't attempt to fill the TLB 517 //or go any further with the memory access |
518 prefetchFaults++; |
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444 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 445 } | 519 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 520 } |
521 522 if (is_fetch) 523 instMisses++; 524 else if (is_write) 525 writeMisses++; 526 else 527 readMisses++; 528 |
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446 // start translation table walk, pass variables rather than 447 // re-retreaving in table walker for speed 448 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 449 vaddr, context_id); 450 fault = tableWalker->walk(req, tc, context_id, mode, translation, 451 timing); 452 if (timing) { 453 delay = true; 454 // for timing mode, return and wait for table walk 455 return fault; 456 } 457 if (fault) 458 return fault; 459 460 te = lookup(vaddr, context_id); 461 if (!te) 462 printTlb(); 463 assert(te); | 529 // start translation table walk, pass variables rather than 530 // re-retreaving in table walker for speed 531 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 532 vaddr, context_id); 533 fault = tableWalker->walk(req, tc, context_id, mode, translation, 534 timing); 535 if (timing) { 536 delay = true; 537 // for timing mode, return and wait for table walk 538 return fault; 539 } 540 if (fault) 541 return fault; 542 543 te = lookup(vaddr, context_id); 544 if (!te) 545 printTlb(); 546 assert(te); |
547 } else { 548 if (is_fetch) 549 instHits++; 550 else if (is_write) 551 writeHits++; 552 else 553 readHits++; |
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464 } 465 466 // Set memory attributes 467 DPRINTF(TLBVerbose, 468 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 469 outerAttrs: %d\n", 470 te->shareable, te->innerAttrs, te->outerAttrs); 471 setAttr(te->attributes); 472 if (te->nonCacheable) 473 req->setFlags(Request::UNCACHEABLE); 474 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 475 switch ( (dacr >> (te->domain * 2)) & 0x3) { 476 case 0: | 554 } 555 556 // Set memory attributes 557 DPRINTF(TLBVerbose, 558 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 559 outerAttrs: %d\n", 560 te->shareable, te->innerAttrs, te->outerAttrs); 561 setAttr(te->attributes); 562 if (te->nonCacheable) 563 req->setFlags(Request::UNCACHEABLE); 564 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 565 switch ( (dacr >> (te->domain * 2)) & 0x3) { 566 case 0: |
567 domainFaults++; |
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477 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 478 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 479 if (is_fetch) 480 return new PrefetchAbort(vaddr, 481 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 482 else 483 return new DataAbort(vaddr, te->domain, is_write, 484 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 58 unchanged lines hidden (view full) --- 543 case 6: 544 case 7: 545 abt = is_write; 546 break; 547 default: 548 panic("Unknown permissions\n"); 549 } 550 if ((is_fetch) && (abt || te->xn)) { | 568 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 569 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 570 if (is_fetch) 571 return new PrefetchAbort(vaddr, 572 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 573 else 574 return new DataAbort(vaddr, te->domain, is_write, 575 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 58 unchanged lines hidden (view full) --- 634 case 6: 635 case 7: 636 abt = is_write; 637 break; 638 default: 639 panic("Unknown permissions\n"); 640 } 641 if ((is_fetch) && (abt || te->xn)) { |
642 permsFaults++; |
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551 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 552 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 553 return new PrefetchAbort(vaddr, 554 (te->sNp ? ArmFault::Permission0 : 555 ArmFault::Permission1)); 556 } else if (abt) { | 643 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 644 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 645 return new PrefetchAbort(vaddr, 646 (te->sNp ? ArmFault::Permission0 : 647 ArmFault::Permission1)); 648 } else if (abt) { |
649 permsFaults++; |
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557 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 558 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 559 return new DataAbort(vaddr, te->domain, is_write, 560 (te->sNp ? ArmFault::Permission0 : 561 ArmFault::Permission1)); 562 } 563 564 req->setPaddr(te->pAddr(vaddr)); --- 46 unchanged lines hidden --- | 650 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 651 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 652 return new DataAbort(vaddr, te->domain, is_write, 653 (te->sNp ? ArmFault::Permission0 : 654 ArmFault::Permission1)); 655 } 656 657 req->setPaddr(te->pAddr(vaddr)); --- 46 unchanged lines hidden --- |