tlb.cc (7406:ddc26bd4ea7d) | tlb.cc (7436:b578349f9371) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 370 unchanged lines hidden (view full) --- 379 req->setFlags(Request::UNCACHEABLE); 380 } else { 381 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 382 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 383 384 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 385 req->setFlags(Request::UNCACHEABLE); 386 } | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 370 unchanged lines hidden (view full) --- 379 req->setFlags(Request::UNCACHEABLE); 380 } else { 381 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 382 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 383 384 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 385 req->setFlags(Request::UNCACHEABLE); 386 } |
387 388 // Set memory attributes 389 TlbEntry temp_te; 390 tableWalker->memAttrs(temp_te, 0, 1); 391 temp_te.shareable = true; 392 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 393 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 394 temp_te.innerAttrs, temp_te.outerAttrs); 395 setAttr(temp_te.attributes); 396 |
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387 return trickBoxCheck(req, mode, 0, false); 388 } 389 390 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 391 // Translation enabled 392 393 TlbEntry *te = lookup(vaddr, context_id); 394 if (te == NULL) { --- 9 unchanged lines hidden (view full) --- 404 return fault; 405 406 te = lookup(vaddr, context_id); 407 if (!te) 408 printTlb(); 409 assert(te); 410 } 411 | 397 return trickBoxCheck(req, mode, 0, false); 398 } 399 400 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 401 // Translation enabled 402 403 TlbEntry *te = lookup(vaddr, context_id); 404 if (te == NULL) { --- 9 unchanged lines hidden (view full) --- 414 return fault; 415 416 te = lookup(vaddr, context_id); 417 if (!te) 418 printTlb(); 419 assert(te); 420 } 421 |
422 // Set memory attributes 423 DPRINTF(TLBVerbose, 424 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 425 outerAttrs: %d\n", 426 te->shareable, te->innerAttrs, te->outerAttrs); 427 setAttr(te->attributes); 428 |
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412 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 413 switch ( (dacr >> (te->domain * 2)) & 0x3) { 414 case 0: 415 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 416 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 417 if (is_fetch) 418 return new PrefetchAbort(vaddr, 419 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 129 unchanged lines hidden --- | 429 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 430 switch ( (dacr >> (te->domain * 2)) & 0x3) { 431 case 0: 432 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 433 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 434 if (is_fetch) 435 return new PrefetchAbort(vaddr, 436 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); --- 129 unchanged lines hidden --- |