tlb.cc (12528:a9960d039c29) | tlb.cc (12735:e3da526a0654) |
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1/* 2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1254 unchanged lines hidden (view full) --- 1263 1264 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 1265 cpsr = tc->readMiscReg(MISCREG_CPSR); 1266 1267 // Dependencies: SCR/SCR_EL3, CPSR 1268 isSecure = inSecureState(tc) && 1269 !(tranType & HypMode) && !(tranType & S1S2NsTran); 1270 | 1/* 2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1254 unchanged lines hidden (view full) --- 1263 1264 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 1265 cpsr = tc->readMiscReg(MISCREG_CPSR); 1266 1267 // Dependencies: SCR/SCR_EL3, CPSR 1268 isSecure = inSecureState(tc) && 1269 !(tranType & HypMode) && !(tranType & S1S2NsTran); 1270 |
1271 const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; 1272 aarch64 = opModeIs64(op_mode) || 1273 (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); | 1271 aarch64EL = tranTypeEL(cpsr, tranType); 1272 aarch64 = isStage2 ? 1273 ELIs64(tc, EL2) : 1274 ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL); |
1274 1275 if (aarch64) { // AArch64 1276 // determine EL we need to translate in | 1275 1276 if (aarch64) { // AArch64 1277 // determine EL we need to translate in |
1277 switch (tranType) { 1278 case S1E0Tran: 1279 case S12E0Tran: 1280 aarch64EL = EL0; 1281 break; 1282 case S1E1Tran: 1283 case S12E1Tran: 1284 aarch64EL = EL1; 1285 break; 1286 case S1E2Tran: 1287 aarch64EL = EL2; 1288 break; 1289 case S1E3Tran: 1290 aarch64EL = EL3; 1291 break; 1292 case NormalTran: 1293 case S1CTran: 1294 case S1S2NsTran: 1295 case HypMode: 1296 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 1297 break; 1298 } 1299 | |
1300 switch (aarch64EL) { 1301 case EL0: 1302 case EL1: 1303 { 1304 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1305 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1306 uint64_t ttbr_asid = ttbcr.a1 ? 1307 tc->readMiscReg(MISCREG_TTBR1_EL1) : --- 83 unchanged lines hidden (view full) --- 1391 directToStage2 = false; 1392 } 1393 } 1394 miscRegValid = true; 1395 miscRegContext = tc->contextId(); 1396 curTranType = tranType; 1397} 1398 | 1278 switch (aarch64EL) { 1279 case EL0: 1280 case EL1: 1281 { 1282 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1283 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1284 uint64_t ttbr_asid = ttbcr.a1 ? 1285 tc->readMiscReg(MISCREG_TTBR1_EL1) : --- 83 unchanged lines hidden (view full) --- 1369 directToStage2 = false; 1370 } 1371 } 1372 miscRegValid = true; 1373 miscRegContext = tc->contextId(); 1374 curTranType = tranType; 1375} 1376 |
1377ExceptionLevel 1378TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type) 1379{ 1380 switch (type) { 1381 case S1E0Tran: 1382 case S12E0Tran: 1383 return EL0; 1384 1385 case S1E1Tran: 1386 case S12E1Tran: 1387 return EL1; 1388 1389 case S1E2Tran: 1390 return EL2; 1391 1392 case S1E3Tran: 1393 return EL3; 1394 1395 case NormalTran: 1396 case S1CTran: 1397 case S1S2NsTran: 1398 case HypMode: 1399 return opModeToEL((OperatingMode)(uint8_t)cpsr.mode); 1400 1401 default: 1402 panic("Unknown translation mode!\n"); 1403 } 1404} 1405 |
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1399Fault 1400TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1401 Translation *translation, bool timing, bool functional, 1402 bool is_secure, TLB::ArmTranslationType tranType) 1403{ 1404 bool is_fetch = (mode == Execute); 1405 bool is_write = (mode == Write); 1406 --- 166 unchanged lines hidden --- | 1406Fault 1407TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1408 Translation *translation, bool timing, bool functional, 1409 bool is_secure, TLB::ArmTranslationType tranType) 1410{ 1411 bool is_fetch = (mode == Execute); 1412 bool is_write = (mode == Write); 1413 --- 166 unchanged lines hidden --- |