tlb.cc (12499:b81688796004) | tlb.cc (12506:aed554105426) |
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1/* 2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 589 unchanged lines hidden (view full) --- 598 req->setPaddr(paddr); 599 600 return finalizePhysical(req, tc, mode); 601} 602 603Fault 604TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 605{ | 1/* 2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 589 unchanged lines hidden (view full) --- 598 req->setPaddr(paddr); 599 600 return finalizePhysical(req, tc, mode); 601} 602 603Fault 604TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 605{ |
606 // a data cache maintenance instruction that operates by MVA does 607 // not generate a Data Abort exeception due to a Permission fault 608 if (req->isCacheMaintenance()) { 609 return NoFault; 610 } 611 |
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606 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 607 Request::Flags flags = req->getFlags(); 608 bool is_fetch = (mode == Execute); 609 bool is_write = (mode == Write); 610 bool is_priv = isPriv && !(flags & UserMode); 611 612 // Get the translation type from the actuall table entry 613 ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran --- 159 unchanged lines hidden (view full) --- 773 774 775Fault 776TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 777 ThreadContext *tc) 778{ 779 assert(aarch64); 780 | 612 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 613 Request::Flags flags = req->getFlags(); 614 bool is_fetch = (mode == Execute); 615 bool is_write = (mode == Write); 616 bool is_priv = isPriv && !(flags & UserMode); 617 618 // Get the translation type from the actuall table entry 619 ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran --- 159 unchanged lines hidden (view full) --- 779 780 781Fault 782TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 783 ThreadContext *tc) 784{ 785 assert(aarch64); 786 |
787 // A data cache maintenance instruction that operates by VA does 788 // not generate a Permission fault unless: 789 // * It is a data cache invalidate (dc ivac) which requires write 790 // permissions to the VA, or 791 // * It is executed from EL0 792 if (req->isCacheClean() && aarch64EL != EL0 && !isStage2) { 793 return NoFault; 794 } 795 |
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781 Addr vaddr_tainted = req->getVaddr(); 782 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 783 784 Request::Flags flags = req->getFlags(); 785 bool is_fetch = (mode == Execute); | 796 Addr vaddr_tainted = req->getVaddr(); 797 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); 798 799 Request::Flags flags = req->getFlags(); 800 bool is_fetch = (mode == Execute); |
786 bool is_write = (mode == Write); | 801 // Cache clean operations require read permissions to the specified VA 802 bool is_write = !req->isCacheClean() && mode == Write; |
787 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 788 789 updateMiscReg(tc, curTranType); 790 791 // If this is the second stage of translation and the request is for a 792 // stage 1 page table walk then we need to check the HCR.PTW bit. This 793 // allows us to generate a fault if the request targets an area marked 794 // as a device or strongly ordered. --- 728 unchanged lines hidden (view full) --- 1523 fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 1524 test = ti; 1525 } 1526} 1527 1528Fault 1529TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 1530{ | 803 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 804 805 updateMiscReg(tc, curTranType); 806 807 // If this is the second stage of translation and the request is for a 808 // stage 1 page table walk then we need to check the HCR.PTW bit. This 809 // allows us to generate a fault if the request targets an area marked 810 // as a device or strongly ordered. --- 728 unchanged lines hidden (view full) --- 1539 fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name()); 1540 test = ti; 1541 } 1542} 1543 1544Fault 1545TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 1546{ |
1531 if (!test || !req->hasSize() || req->getSize() == 0) { | 1547 if (!test || !req->hasSize() || req->getSize() == 0 || 1548 req->isCacheMaintenance()) { |
1532 return NoFault; 1533 } else { 1534 return test->translationCheck(req, isPriv, mode, domain); 1535 } 1536} 1537 1538Fault 1539TLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, --- 16 unchanged lines hidden --- | 1549 return NoFault; 1550 } else { 1551 return test->translationCheck(req, isPriv, mode, domain); 1552 } 1553} 1554 1555Fault 1556TLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, --- 16 unchanged lines hidden --- |