tlb.cc (12005:f4b9607db0af) | tlb.cc (12356:e56e838c47cb) |
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1/* 2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 993 unchanged lines hidden (view full) --- 1002 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 1003 1004 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 1005 "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, 1006 scr, sctlr, flags, tranType); 1007 1008 if ((req->isInstFetch() && (!sctlr.i)) || 1009 ((!req->isInstFetch()) && (!sctlr.c))){ | 1/* 2 * Copyright (c) 2010-2013, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 993 unchanged lines hidden (view full) --- 1002 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 1003 1004 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 1005 "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, 1006 scr, sctlr, flags, tranType); 1007 1008 if ((req->isInstFetch() && (!sctlr.i)) || 1009 ((!req->isInstFetch()) && (!sctlr.c))){ |
1010 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); | 1010 if (!req->isCacheMaintenance()) { 1011 req->setFlags(Request::UNCACHEABLE); 1012 } 1013 req->setFlags(Request::STRICT_ORDER); |
1011 } 1012 if (!is_fetch) { 1013 assert(flags & MustBeOne); 1014 if (sctlr.a || !(flags & AllowUnaligned)) { 1015 if (vaddr & mask(flags & AlignmentMask)) { 1016 alignFaults++; 1017 return std::make_shared<DataAbort>( 1018 vaddr_tainted, --- 9 unchanged lines hidden (view full) --- 1028 1029 req->setPaddr(vaddr); 1030 // When the MMU is off the security attribute corresponds to the 1031 // security state of the processor 1032 if (isSecure) 1033 req->setFlags(Request::SECURE); 1034 1035 // @todo: double check this (ARM ARM issue C B3.2.1) | 1014 } 1015 if (!is_fetch) { 1016 assert(flags & MustBeOne); 1017 if (sctlr.a || !(flags & AllowUnaligned)) { 1018 if (vaddr & mask(flags & AlignmentMask)) { 1019 alignFaults++; 1020 return std::make_shared<DataAbort>( 1021 vaddr_tainted, --- 9 unchanged lines hidden (view full) --- 1031 1032 req->setPaddr(vaddr); 1033 // When the MMU is off the security attribute corresponds to the 1034 // security state of the processor 1035 if (isSecure) 1036 req->setFlags(Request::SECURE); 1037 1038 // @todo: double check this (ARM ARM issue C B3.2.1) |
1036 if (long_desc_format || sctlr.tre == 0) { 1037 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 1038 } else { 1039 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 1040 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); | 1039 if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 || 1040 nmrr.or0 == 0 || prrr.tr0 != 0x2) { 1041 if (!req->isCacheMaintenance()) { 1042 req->setFlags(Request::UNCACHEABLE); 1043 } 1044 req->setFlags(Request::STRICT_ORDER); |
1041 } 1042 1043 // Set memory attributes 1044 TlbEntry temp_te; 1045 temp_te.ns = !isSecure; 1046 if (isStage2 || hcr.dc == 0 || isSecure || 1047 (isHyp && !(tranType & S1CTran))) { 1048 --- 37 unchanged lines hidden (view full) --- 1086 // Set memory attributes 1087 DPRINTF(TLBVerbose, 1088 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1089 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1090 te->shareable, te->innerAttrs, te->outerAttrs, 1091 static_cast<uint8_t>(te->mtype), isStage2); 1092 setAttr(te->attributes); 1093 | 1045 } 1046 1047 // Set memory attributes 1048 TlbEntry temp_te; 1049 temp_te.ns = !isSecure; 1050 if (isStage2 || hcr.dc == 0 || isSecure || 1051 (isHyp && !(tranType & S1CTran))) { 1052 --- 37 unchanged lines hidden (view full) --- 1090 // Set memory attributes 1091 DPRINTF(TLBVerbose, 1092 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1093 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1094 te->shareable, te->innerAttrs, te->outerAttrs, 1095 static_cast<uint8_t>(te->mtype), isStage2); 1096 setAttr(te->attributes); 1097 |
1094 if (te->nonCacheable) | 1098 if (te->nonCacheable && !req->isCacheMaintenance()) |
1095 req->setFlags(Request::UNCACHEABLE); 1096 1097 // Require requests to be ordered if the request goes to 1098 // strongly ordered or device memory (i.e., anything other 1099 // than normal memory requires strict order). 1100 if (te->mtype != TlbEntry::MemoryType::Normal) 1101 req->setFlags(Request::STRICT_ORDER); 1102 --- 448 unchanged lines hidden --- | 1099 req->setFlags(Request::UNCACHEABLE); 1100 1101 // Require requests to be ordered if the request goes to 1102 // strongly ordered or device memory (i.e., anything other 1103 // than normal memory requires strict order). 1104 if (te->mtype != TlbEntry::MemoryType::Normal) 1105 req->setFlags(Request::STRICT_ORDER); 1106 --- 448 unchanged lines hidden --- |