tlb.cc (11575:0005b28685f0) | tlb.cc (11577:a26a328c20eb) |
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1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1206 unchanged lines hidden (view full) --- 1215 isSecure = inSecureState(tc) && 1216 !(tranType & HypMode) && !(tranType & S1S2NsTran); 1217 1218 const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; 1219 aarch64 = opModeIs64(op_mode) || 1220 (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); 1221 1222 if (aarch64) { // AArch64 | 1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1206 unchanged lines hidden (view full) --- 1215 isSecure = inSecureState(tc) && 1216 !(tranType & HypMode) && !(tranType & S1S2NsTran); 1217 1218 const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; 1219 aarch64 = opModeIs64(op_mode) || 1220 (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); 1221 1222 if (aarch64) { // AArch64 |
1223 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; | 1223 // determine EL we need to translate in 1224 switch (tranType) { 1225 case S1E0Tran: 1226 case S12E0Tran: 1227 aarch64EL = EL0; 1228 break; 1229 case S1E1Tran: 1230 case S12E1Tran: 1231 aarch64EL = EL1; 1232 break; 1233 case S1E2Tran: 1234 aarch64EL = EL2; 1235 break; 1236 case S1E3Tran: 1237 aarch64EL = EL3; 1238 break; 1239 case NormalTran: 1240 case S1CTran: 1241 case S1S2NsTran: 1242 case HypMode: 1243 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 1244 break; 1245 } 1246 |
1224 switch (aarch64EL) { 1225 case EL0: 1226 case EL1: 1227 { 1228 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1229 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1230 uint64_t ttbr_asid = ttbcr.a1 ? 1231 tc->readMiscReg(MISCREG_TTBR1_EL1) : --- 21 unchanged lines hidden (view full) --- 1253 isHyp = tranType & HypMode; 1254 isHyp &= (tranType & S1S2NsTran) == 0; 1255 isHyp &= (tranType & S1CTran) == 0; 1256 // Work out if we should skip the first stage of translation and go 1257 // directly to stage 2. This value is cached so we don't have to 1258 // compute it for every translation. 1259 stage2Req = isStage2 || 1260 (hcr.vm && !isHyp && !isSecure && | 1247 switch (aarch64EL) { 1248 case EL0: 1249 case EL1: 1250 { 1251 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1252 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1253 uint64_t ttbr_asid = ttbcr.a1 ? 1254 tc->readMiscReg(MISCREG_TTBR1_EL1) : --- 21 unchanged lines hidden (view full) --- 1276 isHyp = tranType & HypMode; 1277 isHyp &= (tranType & S1S2NsTran) == 0; 1278 isHyp &= (tranType & S1CTran) == 0; 1279 // Work out if we should skip the first stage of translation and go 1280 // directly to stage 2. This value is cached so we don't have to 1281 // compute it for every translation. 1282 stage2Req = isStage2 || 1283 (hcr.vm && !isHyp && !isSecure && |
1261 !(tranType & S1CTran) && (aarch64EL < EL2)); | 1284 !(tranType & S1CTran) && (aarch64EL < EL2) && 1285 !(tranType & S1E1Tran)); // <--- FIX THIS HACK |
1262 directToStage2 = !isStage2 && stage2Req && !sctlr.m; 1263 } else { 1264 vmid = 0; 1265 isHyp = false; 1266 directToStage2 = false; 1267 stage2Req = false; 1268 } 1269 } else { // AArch32 --- 225 unchanged lines hidden --- | 1286 directToStage2 = !isStage2 && stage2Req && !sctlr.m; 1287 } else { 1288 vmid = 0; 1289 isHyp = false; 1290 directToStage2 = false; 1291 stage2Req = false; 1292 } 1293 } else { // AArch32 --- 225 unchanged lines hidden --- |