tlb.cc (11560:f050b8cf4754) | tlb.cc (11575:0005b28685f0) |
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1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 797 unchanged lines hidden (view full) --- 806 uint8_t pxn = te->pxn; 807 bool r = !is_write && !is_fetch; 808 bool w = is_write; 809 bool x = is_fetch; 810 DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 811 "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 812 813 if (isStage2) { | 1/* 2 * Copyright (c) 2010-2013, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 797 unchanged lines hidden (view full) --- 806 uint8_t pxn = te->pxn; 807 bool r = !is_write && !is_fetch; 808 bool w = is_write; 809 bool x = is_fetch; 810 DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 811 "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 812 813 if (isStage2) { |
814 panic("Virtualization in AArch64 state is not supported yet"); | 814 assert(ArmSystem::haveVirtualization(tc) && aarch64EL != EL2); 815 // In stage 2 we use the hypervisor access permission bits. 816 // The following permissions are described in ARM DDI 0487A.f 817 // D4-1802 818 uint8_t hap = 0x3 & te->hap; 819 if (is_fetch) { 820 // sctlr.wxn overrides the xn bit 821 grant = !sctlr.wxn && !xn; 822 } else if (is_write) { 823 grant = hap & 0x2; 824 } else { // is_read 825 grant = hap & 0x1; 826 } |
815 } else { 816 switch (aarch64EL) { 817 case EL0: 818 { 819 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 820 switch (perm) { 821 case 0: 822 case 1: --- 405 unchanged lines hidden (view full) --- 1228 asid = -1; 1229 break; 1230 case EL3: 1231 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 1232 ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 1233 asid = -1; 1234 break; 1235 } | 827 } else { 828 switch (aarch64EL) { 829 case EL0: 830 { 831 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 832 switch (perm) { 833 case 0: 834 case 1: --- 405 unchanged lines hidden (view full) --- 1240 asid = -1; 1241 break; 1242 case EL3: 1243 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 1244 ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 1245 asid = -1; 1246 break; 1247 } |
1248 hcr = tc->readMiscReg(MISCREG_HCR_EL2); |
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1236 scr = tc->readMiscReg(MISCREG_SCR_EL3); 1237 isPriv = aarch64EL != EL0; | 1249 scr = tc->readMiscReg(MISCREG_SCR_EL3); 1250 isPriv = aarch64EL != EL0; |
1238 // @todo: modify this behaviour to support Virtualization in 1239 // AArch64 1240 vmid = 0; 1241 isHyp = false; 1242 directToStage2 = false; 1243 stage2Req = false; | 1251 if (haveVirtualization) { 1252 vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); 1253 isHyp = tranType & HypMode; 1254 isHyp &= (tranType & S1S2NsTran) == 0; 1255 isHyp &= (tranType & S1CTran) == 0; 1256 // Work out if we should skip the first stage of translation and go 1257 // directly to stage 2. This value is cached so we don't have to 1258 // compute it for every translation. 1259 stage2Req = isStage2 || 1260 (hcr.vm && !isHyp && !isSecure && 1261 !(tranType & S1CTran) && (aarch64EL < EL2)); 1262 directToStage2 = !isStage2 && stage2Req && !sctlr.m; 1263 } else { 1264 vmid = 0; 1265 isHyp = false; 1266 directToStage2 = false; 1267 stage2Req = false; 1268 } |
1244 } else { // AArch32 1245 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 1246 !isSecure)); 1247 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 1248 !isSecure)); 1249 scr = tc->readMiscReg(MISCREG_SCR); 1250 isPriv = cpsr.mode != MODE_USER; 1251 if (longDescFormatInUse(tc)) { --- 105 unchanged lines hidden (view full) --- 1357} 1358 1359Fault 1360TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1361 Translation *translation, bool timing, bool functional, 1362 TlbEntry *mergeTe) 1363{ 1364 Fault fault; | 1269 } else { // AArch32 1270 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 1271 !isSecure)); 1272 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 1273 !isSecure)); 1274 scr = tc->readMiscReg(MISCREG_SCR); 1275 isPriv = cpsr.mode != MODE_USER; 1276 if (longDescFormatInUse(tc)) { --- 105 unchanged lines hidden (view full) --- 1382} 1383 1384Fault 1385TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1386 Translation *translation, bool timing, bool functional, 1387 TlbEntry *mergeTe) 1388{ 1389 Fault fault; |
1390 1391 if (isStage2) { 1392 // We are already in the stage 2 TLB. Grab the table entry for stage 1393 // 2 only. We are here because stage 1 translation is disabled. 1394 TlbEntry *s2Te = NULL; 1395 // Get the stage 2 table entry 1396 fault = getTE(&s2Te, req, tc, mode, translation, timing, functional, 1397 isSecure, curTranType); 1398 // Check permissions of stage 2 1399 if ((s2Te != NULL) && (fault = NoFault)) { 1400 if(aarch64) 1401 fault = checkPermissions64(s2Te, req, mode, tc); 1402 else 1403 fault = checkPermissions(s2Te, req, mode); 1404 } 1405 *te = s2Te; 1406 return fault; 1407 } 1408 |
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1365 TlbEntry *s1Te = NULL; 1366 1367 Addr vaddr_tainted = req->getVaddr(); 1368 1369 // Get the stage 1 table entry 1370 fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 1371 isSecure, curTranType); 1372 // only proceed if we have a valid table entry --- 78 unchanged lines hidden --- | 1409 TlbEntry *s1Te = NULL; 1410 1411 Addr vaddr_tainted = req->getVaddr(); 1412 1413 // Get the stage 1 table entry 1414 fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 1415 isSecure, curTranType); 1416 // only proceed if we have a valid table entry --- 78 unchanged lines hidden --- |