tlb.cc (10824:308771bd2647) | tlb.cc (10825:5d059b8ed8a4) |
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1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1062 unchanged lines hidden (view full) --- 1071 DPRINTF(TLBVerbose, 1072 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1073 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1074 te->shareable, te->innerAttrs, te->outerAttrs, 1075 static_cast<uint8_t>(te->mtype), isStage2); 1076 setAttr(te->attributes); 1077 1078 if (te->nonCacheable) | 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1062 unchanged lines hidden (view full) --- 1071 DPRINTF(TLBVerbose, 1072 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1073 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1074 te->shareable, te->innerAttrs, te->outerAttrs, 1075 static_cast<uint8_t>(te->mtype), isStage2); 1076 setAttr(te->attributes); 1077 1078 if (te->nonCacheable) |
1079 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); | 1079 req->setFlags(Request::UNCACHEABLE); |
1080 | 1080 |
1081 // Require requests to be ordered if the request goes to 1082 // strongly ordered or device memory (i.e., anything other 1083 // than normal memory requires strict order). 1084 if (te->mtype != TlbEntry::MemoryType::Normal) 1085 req->setFlags(Request::STRICT_ORDER); 1086 |
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1081 Addr pa = te->pAddr(vaddr); 1082 req->setPaddr(pa); 1083 1084 if (isSecure && !te->ns) { 1085 req->setFlags(Request::SECURE); 1086 } 1087 if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 1088 (te->mtype != TlbEntry::MemoryType::Normal)) { --- 343 unchanged lines hidden --- | 1087 Addr pa = te->pAddr(vaddr); 1088 req->setPaddr(pa); 1089 1090 if (isSecure && !te->ns) { 1091 req->setFlags(Request::SECURE); 1092 } 1093 if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 1094 (te->mtype != TlbEntry::MemoryType::Normal)) { --- 343 unchanged lines hidden --- |