1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Checkpoint.hh"
57#include "debug/TLB.hh"
58#include "debug/TLBVerbose.hh"
59#include "mem/page_table.hh"
60#include "params/ArmTLB.hh"
61#include "sim/process.hh"
62
63#if FULL_SYSTEM
64#include "arch/arm/system.hh"
65#include "arch/arm/table_walker.hh"
66#endif
67
68using namespace std;
69using namespace ArmISA;
70
71TLB::TLB(const Params *p)
72 : BaseTLB(p), size(p->size)
73#if FULL_SYSTEM
74 , tableWalker(p->walker)
75#endif
76 , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
77{
78 table = new TlbEntry[size];
79 memset(table, 0, sizeof(TlbEntry) * size);
80
81#if FULL_SYSTEM
82 tableWalker->setTlb(this);
83#endif
84}
85
86TLB::~TLB()
87{
88 if (table)
89 delete [] table;
90}
91
92bool
93TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
94{
95 if (!miscRegValid)
96 updateMiscReg(tc);
97 TlbEntry *e = lookup(va, contextId, true);
98 if (!e)
99 return false;
100 pa = e->pAddr(va);
101 return true;
102}
103
104TlbEntry*
105TLB::lookup(Addr va, uint8_t cid, bool functional)
106{
107
108 TlbEntry *retval = NULL;
109
110 // Maitaining LRU array
111
112 int x = 0;
113 while (retval == NULL && x < size) {
114 if (table[x].match(va, cid)) {
115
116 // We only move the hit entry ahead when the position is higher than rangeMRU
117 if (x > rangeMRU) {
118 TlbEntry tmp_entry = table[x];
119 for(int i = x; i > 0; i--)
120 table[i] = table[i-1];
121 table[0] = tmp_entry;
122 retval = &table[0];
123 } else {
124 retval = &table[x];
125 }
126 break;
127 }
128 x++;
129 }
130
131 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
132 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
133 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
134 retval ? retval->ap : 0);
135 ;
136 return retval;
137}
138
139// insert a new TLB entry
140void
141TLB::insert(Addr addr, TlbEntry &entry)
142{
143 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
144 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
145 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
146 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
147 entry.xn, entry.ap, entry.domain);
148
149 if (table[size-1].valid)
150 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
151 table[size-1].vpn << table[size-1].N, table[size-1].asid,
152 table[size-1].pfn << table[size-1].N, table[size-1].size,
153 table[size-1].ap);
154
155 //inserting to MRU position and evicting the LRU one
156
157 for(int i = size-1; i > 0; i--)
158 table[i] = table[i-1];
159 table[0] = entry;
160
161 inserts++;
162}
163
164void
165TLB::printTlb()
166{
167 int x = 0;
168 TlbEntry *te;
169 DPRINTF(TLB, "Current TLB contents:\n");
170 while (x < size) {
171 te = &table[x];
172 if (te->valid)
173 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
174 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
175 x++;
176 }
177}
178
179
180void
181TLB::flushAll()
182{
183 DPRINTF(TLB, "Flushing all TLB entries\n");
184 int x = 0;
185 TlbEntry *te;
186 while (x < size) {
187 te = &table[x];
188 if (te->valid) {
189 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
190 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
191 flushedEntries++;
192 }
193 x++;
194 }
195
196 memset(table, 0, sizeof(TlbEntry) * size);
197
198 flushTlb++;
199}
200
201
202void
203TLB::flushMvaAsid(Addr mva, uint64_t asn)
204{
205 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
206 TlbEntry *te;
207
208 te = lookup(mva, asn);
209 while (te != NULL) {
210 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
211 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
212 te->valid = false;
213 flushedEntries++;
214 te = lookup(mva,asn);
215 }
216 flushTlbMvaAsid++;
217}
218
219void
220TLB::flushAsid(uint64_t asn)
221{
222 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
223
224 int x = 0;
225 TlbEntry *te;
226
227 while (x < size) {
228 te = &table[x];
229 if (te->asid == asn) {
230 te->valid = false;
231 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
232 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
233 flushedEntries++;
234 }
235 x++;
236 }
237 flushTlbAsid++;
238}
239
240void
241TLB::flushMva(Addr mva)
242{
243 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
244
245 int x = 0;
246 TlbEntry *te;
247
248 while (x < size) {
249 te = &table[x];
250 Addr v = te->vpn << te->N;
251 if (mva >= v && mva < v + te->size) {
252 te->valid = false;
253 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
254 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
255 flushedEntries++;
256 }
257 x++;
258 }
259 flushTlbMva++;
260}
261
262void
263TLB::serialize(ostream &os)
264{
265 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
266
267 SERIALIZE_SCALAR(_attr);
268
269 int num_entries = size;
270 SERIALIZE_SCALAR(num_entries);
271 for(int i = 0; i < size; i++){
272 nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
273 table[i].serialize(os);
274 }
275}
276
277void
278TLB::unserialize(Checkpoint *cp, const string &section)
279{
280 DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
281
282 UNSERIALIZE_SCALAR(_attr);
283 int num_entries;
284 UNSERIALIZE_SCALAR(num_entries);
285 for(int i = 0; i < min(size, num_entries); i++){
286 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
287 }
288 miscRegValid = false;
289}
290
291void
292TLB::regStats()
293{
294 instHits
295 .name(name() + ".inst_hits")
296 .desc("ITB inst hits")
297 ;
298
299 instMisses
300 .name(name() + ".inst_misses")
301 .desc("ITB inst misses")
302 ;
303
304 instAccesses
305 .name(name() + ".inst_accesses")
306 .desc("ITB inst accesses")
307 ;
308
309 readHits
310 .name(name() + ".read_hits")
311 .desc("DTB read hits")
312 ;
313
314 readMisses
315 .name(name() + ".read_misses")
316 .desc("DTB read misses")
317 ;
318
319 readAccesses
320 .name(name() + ".read_accesses")
321 .desc("DTB read accesses")
322 ;
323
324 writeHits
325 .name(name() + ".write_hits")
326 .desc("DTB write hits")
327 ;
328
329 writeMisses
330 .name(name() + ".write_misses")
331 .desc("DTB write misses")
332 ;
333
334 writeAccesses
335 .name(name() + ".write_accesses")
336 .desc("DTB write accesses")
337 ;
338
339 hits
340 .name(name() + ".hits")
341 .desc("DTB hits")
342 ;
343
344 misses
345 .name(name() + ".misses")
346 .desc("DTB misses")
347 ;
348
349 accesses
350 .name(name() + ".accesses")
351 .desc("DTB accesses")
352 ;
353
354 flushTlb
355 .name(name() + ".flush_tlb")
356 .desc("Number of times complete TLB was flushed")
357 ;
358
359 flushTlbMva
360 .name(name() + ".flush_tlb_mva")
361 .desc("Number of times TLB was flushed by MVA")
362 ;
363
364 flushTlbMvaAsid
365 .name(name() + ".flush_tlb_mva_asid")
366 .desc("Number of times TLB was flushed by MVA & ASID")
367 ;
368
369 flushTlbAsid
370 .name(name() + ".flush_tlb_asid")
371 .desc("Number of times TLB was flushed by ASID")
372 ;
373
374 flushedEntries
375 .name(name() + ".flush_entries")
376 .desc("Number of entries that have been flushed from TLB")
377 ;
378
379 alignFaults
380 .name(name() + ".align_faults")
381 .desc("Number of TLB faults due to alignment restrictions")
382 ;
383
384 prefetchFaults
385 .name(name() + ".prefetch_faults")
386 .desc("Number of TLB faults due to prefetch")
387 ;
388
389 domainFaults
390 .name(name() + ".domain_faults")
391 .desc("Number of TLB faults due to domain restrictions")
392 ;
393
394 permsFaults
395 .name(name() + ".perms_faults")
396 .desc("Number of TLB faults due to permissions restrictions")
397 ;
398
399 instAccesses = instHits + instMisses;
400 readAccesses = readHits + readMisses;
401 writeAccesses = writeHits + writeMisses;
402 hits = readHits + writeHits + instHits;
403 misses = readMisses + writeMisses + instMisses;
404 accesses = readAccesses + writeAccesses + instAccesses;
405}
406
407#if !FULL_SYSTEM
408Fault
409TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
410 Translation *translation, bool &delay, bool timing)
411{
412 if (!miscRegValid)
413 updateMiscReg(tc);
414 Addr vaddr = req->getVaddr();
415 uint32_t flags = req->getFlags();
416
417 bool is_fetch = (mode == Execute);
418 bool is_write = (mode == Write);
419
420 if (!is_fetch) {
421 assert(flags & MustBeOne);
422 if (sctlr.a || !(flags & AllowUnaligned)) {
423 if (vaddr & flags & AlignmentMask) {
424 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
425 }
426 }
427 }
428
429 Addr paddr;
430 Process *p = tc->getProcessPtr();
431
432 if (!p->pTable->translate(vaddr, paddr))
433 return Fault(new GenericPageTableFault(vaddr));
434 req->setPaddr(paddr);
435
436 return NoFault;
437}
438
439#else // FULL_SYSTEM
440
441Fault
442TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
443{
444 return NoFault;
445}
446
447Fault
448TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
449 bool is_write, uint8_t domain, bool sNp)
450{
451 return NoFault;
452}
453
454Fault
455TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
456 Translation *translation, bool &delay, bool timing)
457{
458 if (!miscRegValid) {
459 updateMiscReg(tc);
460 DPRINTF(TLBVerbose, "TLB variables changed!\n");
461 }
462
463 Addr vaddr = req->getVaddr();
464 uint32_t flags = req->getFlags();
465
466 bool is_fetch = (mode == Execute);
467 bool is_write = (mode == Write);
468 bool is_priv = isPriv && !(flags & UserMode);
469
470 req->setAsid(contextId.asid);
471
472 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
473 isPriv, flags & UserMode);
474 // If this is a clrex instruction, provide a PA of 0 with no fault
475 // This will force the monitor to set the tracked address to 0
476 // a bit of a hack but this effectively clrears this processors monitor
477 if (flags & Request::CLEAR_LL){
478 req->setPaddr(0);
479 req->setFlags(Request::UNCACHEABLE);
480 req->setFlags(Request::CLEAR_LL);
481 return NoFault;
482 }
483 if ((req->isInstFetch() && (!sctlr.i)) ||
484 ((!req->isInstFetch()) && (!sctlr.c))){
485 req->setFlags(Request::UNCACHEABLE);
486 }
487 if (!is_fetch) {
488 assert(flags & MustBeOne);
489 if (sctlr.a || !(flags & AllowUnaligned)) {
490 if (vaddr & flags & AlignmentMask) {
491 alignFaults++;
492 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
493 }
494 }
495 }
496
497 Fault fault;
498
499 if (!sctlr.m) {
500 req->setPaddr(vaddr);
501 if (sctlr.tre == 0) {
502 req->setFlags(Request::UNCACHEABLE);
503 } else {
504 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
505 req->setFlags(Request::UNCACHEABLE);
506 }
507
508 // Set memory attributes
509 TlbEntry temp_te;
510 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
511 temp_te.shareable = true;
512 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
513 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
514 temp_te.innerAttrs, temp_te.outerAttrs);
515 setAttr(temp_te.attributes);
516
517 return trickBoxCheck(req, mode, 0, false);
518 }
519
520 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
521 // Translation enabled
522
523 TlbEntry *te = lookup(vaddr, contextId);
524 if (te == NULL) {
525 if (req->isPrefetch()){
526 //if the request is a prefetch don't attempt to fill the TLB
527 //or go any further with the memory access
528 prefetchFaults++;
529 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
530 }
531
532 if (is_fetch)
533 instMisses++;
534 else if (is_write)
535 writeMisses++;
536 else
537 readMisses++;
538
539 // start translation table walk, pass variables rather than
540 // re-retreaving in table walker for speed
541 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
542 vaddr, contextId);
543 fault = tableWalker->walk(req, tc, contextId, mode, translation,
544 timing);
545 if (timing && fault == NoFault) {
546 delay = true;
547 // for timing mode, return and wait for table walk
548 return fault;
549 }
550 if (fault)
551 return fault;
552
553 te = lookup(vaddr, contextId);
554 if (!te)
555 printTlb();
556 assert(te);
557 } else {
558 if (is_fetch)
559 instHits++;
560 else if (is_write)
561 writeHits++;
562 else
563 readHits++;
564 }
565
566 // Set memory attributes
567 DPRINTF(TLBVerbose,
568 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
569 outerAttrs: %d\n",
570 te->shareable, te->innerAttrs, te->outerAttrs);
571 setAttr(te->attributes);
572 if (te->nonCacheable) {
573 req->setFlags(Request::UNCACHEABLE);
574
575 // Prevent prefetching from I/O devices.
576 if (req->isPrefetch()) {
577 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
578 }
579 }
580
581
582 if (!bootUncacheability &&
583 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
584 req->setFlags(Request::UNCACHEABLE);
585
586 switch ( (dacr >> (te->domain * 2)) & 0x3) {
587 case 0:
588 domainFaults++;
589 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
590 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
591 if (is_fetch)
592 return new PrefetchAbort(vaddr,
593 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
594 else
595 return new DataAbort(vaddr, te->domain, is_write,
596 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
597 case 1:
598 // Continue with permissions check
599 break;
600 case 2:
601 panic("UNPRED domain\n");
602 case 3:
603 req->setPaddr(te->pAddr(vaddr));
604 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
605 if (fault)
606 return fault;
607 return NoFault;
608 }
609
610 uint8_t ap = te->ap;
611
612 if (sctlr.afe == 1)
613 ap |= 1;
614
615 bool abt;
616
617 /* if (!sctlr.xp)
618 ap &= 0x3;
619*/
620 switch (ap) {
621 case 0:
622 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
623 if (!sctlr.xp) {
624 switch ((int)sctlr.rs) {
625 case 2:
626 abt = is_write;
627 break;
628 case 1:
629 abt = is_write || !is_priv;
630 break;
631 case 0:
632 case 3:
633 default:
634 abt = true;
635 break;
636 }
637 } else {
638 abt = true;
639 }
640 break;
641 case 1:
642 abt = !is_priv;
643 break;
644 case 2:
645 abt = !is_priv && is_write;
646 break;
647 case 3:
648 abt = false;
649 break;
650 case 4:
651 panic("UNPRED premissions\n");
652 case 5:
653 abt = !is_priv || is_write;
654 break;
655 case 6:
656 case 7:
657 abt = is_write;
658 break;
659 default:
660 panic("Unknown permissions\n");
661 }
662 if ((is_fetch) && (abt || te->xn)) {
663 permsFaults++;
664 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
665 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
666 return new PrefetchAbort(vaddr,
667 (te->sNp ? ArmFault::Permission0 :
668 ArmFault::Permission1));
669 } else if (abt) {
670 permsFaults++;
671 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
672 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
673 return new DataAbort(vaddr, te->domain, is_write,
674 (te->sNp ? ArmFault::Permission0 :
675 ArmFault::Permission1));
676 }
677
678 req->setPaddr(te->pAddr(vaddr));
679 // Check for a trickbox generated address fault
680 fault = trickBoxCheck(req, mode, te->domain, te->sNp);
681 if (fault)
682 return fault;
683
684 return NoFault;
685}
686
687#endif
688
689Fault
690TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
691{
692 bool delay = false;
693 Fault fault;
694#if FULL_SYSTEM
695 fault = translateFs(req, tc, mode, NULL, delay, false);
696#else
697 fault = translateSe(req, tc, mode, NULL, delay, false);
698#endif
699 assert(!delay);
700 return fault;
701}
702
703Fault
704TLB::translateTiming(RequestPtr req, ThreadContext *tc,
705 Translation *translation, Mode mode)
706{
707 assert(translation);
708 bool delay = false;
709 Fault fault;
710#if FULL_SYSTEM
711 fault = translateFs(req, tc, mode, translation, delay, true);
712#else
713 fault = translateSe(req, tc, mode, translation, delay, true);
714#endif
715 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
716 NoFault);
717 if (!delay)
718 translation->finish(fault, req, tc, mode);
719 else
720 translation->markDelayed();
721 return fault;
722}
723
724Port*
725TLB::getPort()
726{
727#if FULL_SYSTEM
728 return tableWalker->getPort("port");
729#else
730 return NULL;
731#endif
732}
733
734
735
736ArmISA::TLB *
737ArmTLBParams::create()
738{
739 return new ArmISA::TLB(this);
740}