1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 138 unchanged lines hidden (view full) ---

147 table[size-1].pfn << table[size-1].N, table[size-1].size,
148 table[size-1].ap);
149
150 //inserting to MRU position and evicting the LRU one
151
152 for(int i = size-1; i > 0; i--)
153 table[i] = table[i-1];
154 table[0] = entry;
155}
156
157void
158TLB::printTlb()
159{
160 int x = 0;
161 TlbEntry *te;
162 DPRINTF(TLB, "Current TLB contents:\n");

--- 10 unchanged lines hidden (view full) ---

173void
174TLB::flushAll()
175{
176 DPRINTF(TLB, "Flushing all TLB entries\n");
177 int x = 0;
178 TlbEntry *te;
179 while (x < size) {
180 te = &table[x];
181 if (te->valid)
182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
184 x++;
185 }
186
187 memset(table, 0, sizeof(TlbEntry[size]));
188}
189
190
191void
192TLB::flushMvaAsid(Addr mva, uint64_t asn)
193{
194 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
195 TlbEntry *te;
196
197 te = lookup(mva, asn);
198 while (te != NULL) {
199 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
200 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
201 te->valid = false;
202 te = lookup(mva,asn);
203 }
204}
205
206void
207TLB::flushAsid(uint64_t asn)
208{
209 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
210
211 int x = 0;
212 TlbEntry *te;
213
214 while (x < size) {
215 te = &table[x];
216 if (te->asid == asn) {
217 te->valid = false;
218 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
219 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
220 }
221 x++;
222 }
223}
224
225void
226TLB::flushMva(Addr mva)
227{
228 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
229
230 int x = 0;
231 TlbEntry *te;
232
233 while (x < size) {
234 te = &table[x];
235 Addr v = te->vpn << te->N;
236 if (mva >= v && mva < v + te->size) {
237 te->valid = false;
238 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
239 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
240 }
241 x++;
242 }
243}
244
245void
246TLB::serialize(ostream &os)
247{
248 DPRINTF(Checkpoint, "Serializing Arm TLB\n");
249
250 SERIALIZE_SCALAR(_attr);

--- 12 unchanged lines hidden (view full) ---

263 for(int i = 0; i < size; i++){
264 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
265 }
266}
267
268void
269TLB::regStats()
270{
271 read_hits
272 .name(name() + ".read_hits")
273 .desc("DTB read hits")
274 ;
275
276 read_misses
277 .name(name() + ".read_misses")
278 .desc("DTB read misses")
279 ;
280
281
282 read_accesses
283 .name(name() + ".read_accesses")
284 .desc("DTB read accesses")
285 ;
286
287 write_hits
288 .name(name() + ".write_hits")
289 .desc("DTB write hits")
290 ;
291
292 write_misses
293 .name(name() + ".write_misses")
294 .desc("DTB write misses")
295 ;
296
297
298 write_accesses
299 .name(name() + ".write_accesses")
300 .desc("DTB write accesses")
301 ;
302
303 hits
304 .name(name() + ".hits")
305 .desc("DTB hits")
306 ;
307
308 misses
309 .name(name() + ".misses")
310 .desc("DTB misses")
311 ;
312
313 accesses
314 .name(name() + ".accesses")
315 .desc("DTB accesses")
316 ;
317
318 hits = read_hits + write_hits;
319 misses = read_misses + write_misses;
320 accesses = read_accesses + write_accesses;
321}
322
323#if !FULL_SYSTEM
324Fault
325TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
326 Translation *translation, bool &delay, bool timing)
327{
328 // XXX Cache misc registers and have miscreg write function inv cache

--- 66 unchanged lines hidden (view full) ---

395 if ((req->isInstFetch() && (!sctlr.i)) ||
396 ((!req->isInstFetch()) && (!sctlr.c))){
397 req->setFlags(Request::UNCACHEABLE);
398 }
399 if (!is_fetch) {
400 assert(flags & MustBeOne);
401 if (sctlr.a || !(flags & AllowUnaligned)) {
402 if (vaddr & flags & AlignmentMask) {
403 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
404 }
405 }
406 }
407
408 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
409 Fault fault;
410

--- 25 unchanged lines hidden (view full) ---

436 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
437 // Translation enabled
438
439 TlbEntry *te = lookup(vaddr, context_id);
440 if (te == NULL) {
441 if (req->isPrefetch()){
442 //if the request is a prefetch don't attempt to fill the TLB
443 //or go any further with the memory access
444 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
445 }
446 // start translation table walk, pass variables rather than
447 // re-retreaving in table walker for speed
448 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
449 vaddr, context_id);
450 fault = tableWalker->walk(req, tc, context_id, mode, translation,
451 timing);
452 if (timing) {
453 delay = true;
454 // for timing mode, return and wait for table walk
455 return fault;
456 }
457 if (fault)
458 return fault;
459
460 te = lookup(vaddr, context_id);
461 if (!te)
462 printTlb();
463 assert(te);
464 }
465
466 // Set memory attributes
467 DPRINTF(TLBVerbose,
468 "Setting memory attributes: shareable: %d, innerAttrs: %d, \
469 outerAttrs: %d\n",
470 te->shareable, te->innerAttrs, te->outerAttrs);
471 setAttr(te->attributes);
472 if (te->nonCacheable)
473 req->setFlags(Request::UNCACHEABLE);
474 uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
475 switch ( (dacr >> (te->domain * 2)) & 0x3) {
476 case 0:
477 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
478 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
479 if (is_fetch)
480 return new PrefetchAbort(vaddr,
481 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
482 else
483 return new DataAbort(vaddr, te->domain, is_write,
484 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));

--- 58 unchanged lines hidden (view full) ---

543 case 6:
544 case 7:
545 abt = is_write;
546 break;
547 default:
548 panic("Unknown permissions\n");
549 }
550 if ((is_fetch) && (abt || te->xn)) {
551 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
552 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
553 return new PrefetchAbort(vaddr,
554 (te->sNp ? ArmFault::Permission0 :
555 ArmFault::Permission1));
556 } else if (abt) {
557 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
558 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
559 return new DataAbort(vaddr, te->domain, is_write,
560 (te->sNp ? ArmFault::Permission0 :
561 ArmFault::Permission1));
562 }
563
564 req->setPaddr(te->pAddr(vaddr));

--- 46 unchanged lines hidden ---