1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68 : BaseTLB(p), size(p->size), nlu(0)
69#if FULL_SYSTEM
70 , tableWalker(p->walker)
71#endif
72{
73 table = new TlbEntry[size];
74 memset(table, 0, sizeof(TlbEntry[size]));
75
76#if FULL_SYSTEM
77 tableWalker->setTlb(this);
78#endif
79}

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93 return false;
94 pa = e->pAddr(va);
95 return true;
96}
97
98TlbEntry*
99TLB::lookup(Addr va, uint8_t cid, bool functional)
100{
101 // XXX This should either turn into a TlbMap or add caching
102
103 TlbEntry *retval = NULL;
104
105 // Do some kind of caching, fast indexing, anything
106
107 int x = 0;
108 while (retval == NULL && x < size) {
109 if (table[x].match(va, cid)) {
110 retval = &table[x];
111 if (x == nlu && !functional)
112 nextnlu();
113
114 break;
115 }
116 x++;
117 }
118
119 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
120 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
121 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,

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129TLB::insert(Addr addr, TlbEntry &entry)
130{
131 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
132 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
133 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
134 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
135 entry.xn, entry.ap, entry.domain);
136
137 if (table[nlu].valid)
138 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
139 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N,
140 table[nlu].size, table[nlu].ap);
141
142 // XXX Update caching, lookup table etc
143 table[nlu] = entry;
144
145 // XXX Figure out how entries are generally inserted in ARM
146 nextnlu();
147}
148
149void
150TLB::printTlb()
151{
152 int x = 0;
153 TlbEntry *te;
154 DPRINTF(TLB, "Current TLB contents:\n");

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172 te = &table[x];
173 if (te->valid)
174 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
175 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
176 x++;
177 }
178
179 memset(table, 0, sizeof(TlbEntry[size]));
180 nlu = 0;
181}
182
183
184void
185TLB::flushMvaAsid(Addr mva, uint64_t asn)
186{
187 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
188 TlbEntry *te;

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