1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/table_walker.hh"
51#include "arch/arm/tlb.hh"
52#include "arch/arm/utility.hh"
53#include "base/inifile.hh"
54#include "base/str.hh"
55#include "base/trace.hh"
56#include "cpu/thread_context.hh"
57#include "mem/page_table.hh"
58#include "params/ArmTLB.hh"
59#include "sim/process.hh"
60
61using namespace std;
62using namespace ArmISA;
63
64TLB::TLB(const Params *p)
65 : BaseTLB(p), size(p->size), nlu(0)
66#if FULL_SYSTEM
67 , tableWalker(p->walker)
68#endif
69{
70 table = new TlbEntry[size];
71 memset(table, 0, sizeof(TlbEntry[size]));
72
73 tableWalker->setTlb(this);
74}
75
76TLB::~TLB()
77{
78 if (table)
79 delete [] table;
80}
81

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287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295Fault
296TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
297{
298 return NoFault;
299}
300
301Fault
302TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
303 uint8_t domain, bool sNp)
304{
305 return NoFault;
306}
307
308#if !FULL_SYSTEM
309Fault
310TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
311 Translation *translation, bool &delay, bool timing)
312{
313 // XXX Cache misc registers and have miscreg write function inv cache
314 Addr vaddr = req->getVaddr() & ~PcModeMask;
315 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);

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335 req->setPaddr(paddr);
336
337 return NoFault;
338}
339
340#else // FULL_SYSTEM
341
342Fault
343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
344 Translation *translation, bool &delay, bool timing)
345{
346 // XXX Cache misc registers and have miscreg write function inv cache
347 Addr vaddr = req->getVaddr() & ~PcModeMask;
348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 uint32_t flags = req->getFlags();

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430
431 uint8_t ap = te->ap;
432
433 if (sctlr.afe == 1)
434 ap |= 1;
435
436 bool abt;
437
438 switch (ap) {
439 case 0:
440 abt = true;
441 break;
442 case 1:
443 abt = !is_priv;
444 break;
445 case 2:
446 abt = !is_priv && is_write;
447 break;
448 case 3:

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