1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42 * Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60
61using namespace std;
62using namespace ArmISA;
63
64TLB::TLB(const Params *p)
65 : BaseTLB(p), size(p->size), nlu(0)
66{
67 table = new ArmISA::PTE[size];
68 memset(table, 0, sizeof(ArmISA::PTE[size]));
69
70}
71
72TLB::~TLB()
73{
74 if (table)
75 delete [] table;
76}
77
78ArmISA::PTE *
79TLB::lookup(Addr vpn, uint8_t asn) const
80{
81 panic("lookup() not implemented for ARM\n");
82}
83
84// insert a new TLB entry
85void
86TLB::insert(Addr addr, ArmISA::PTE &pte)
87{
88 fatal("TLB Insert not yet implemented\n");
89}
90
91void
92TLB::flushAll()
93{
94 DPRINTF(TLB, "flushAll\n");
95 memset(table, 0, sizeof(ArmISA::PTE[size]));
96 lookupTable.clear();
97 nlu = 0;
98}
99
100void
101TLB::serialize(ostream &os)
102{
103 SERIALIZE_SCALAR(size);
104 SERIALIZE_SCALAR(nlu);
105
106 for (int i = 0; i < size; i++) {
107 nameOut(os, csprintf("%s.PTE%d", name(), i));
108 table[i].serialize(os);
109 }
110}
111
112void
113TLB::unserialize(Checkpoint *cp, const string &section)
114{
115 UNSERIALIZE_SCALAR(size);
116 UNSERIALIZE_SCALAR(nlu);
117
118 panic("Need to properly unserialize TLB\n");
119 for (int i = 0; i < size; i++) {
120 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
121 }
122}
123
124void
125TLB::regStats()
126{
127 read_hits
128 .name(name() + ".read_hits")
129 .desc("DTB read hits")

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177 ;
178
179 hits = read_hits + write_hits;
180 misses = read_misses + write_misses;
181 accesses = read_accesses + write_accesses;
182}
183
184Fault
185TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
186{
187 Addr vaddr = req->getVaddr() & ~PcModeMask;
188 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
189 uint32_t flags = req->getFlags();
190
191 if (mode != Execute) {
192 assert(flags & MustBeOne);
193
194 if (sctlr.a || (flags & AllowUnaligned) == 0) {
195 if ((vaddr & flags & AlignmentMask) != 0) {
196 return new DataAbort(vaddr, (mode == Write), 0,
197 ArmFault::AlignmentFault);
198 }
199 }
200 }
201#if !FULL_SYSTEM
202 Process * p = tc->getProcessPtr();
203
204 Addr paddr;
205 if (!p->pTable->translate(vaddr, paddr))
206 return Fault(new GenericPageTableFault(vaddr));
207 req->setPaddr(paddr);
208
209 return NoFault;
210#else
211 if (!sctlr.m) {
212 req->setPaddr(vaddr);
213 return NoFault;
214 }
215 warn_once("MPU translation not implemented\n");
216 req->setPaddr(vaddr);
217 return NoFault;
218
219
220#endif
221}
222
223void
224TLB::translateTiming(RequestPtr req, ThreadContext *tc,
225 Translation *translation, Mode mode)
226{
227 assert(translation);
228 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
229}
230
231ArmISA::TLB *
232ArmTLBParams::create()
233{
234 return new ArmISA::TLB(this);
235}