1/*
2 * Copyright (c) 2010-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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128 aarch64 ? aarch64EL : EL1);
129 if (!e)
130 return false;
131 pa = e->pAddr(va);
132 return true;
133}
134
135Fault
136TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
137{
138 const Addr paddr = req->getPaddr();
139
140 if (m5opRange.contains(paddr)) {
141 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
142 req->setPaddr(GenericISA::iprAddressPseudoInst(
143 (paddr >> 8) & 0xFF,
144 paddr & 0xFF));

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556
557void
558TLB::regProbePoints()
559{
560 ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
561}
562
563Fault
564TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
565 Translation *translation, bool &delay, bool timing)
566{
567 updateMiscReg(tc);
568 Addr vaddr_tainted = req->getVaddr();
569 Addr vaddr = 0;
570 if (aarch64)
571 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
572 else

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596 if (!p->pTable->translate(vaddr, paddr))
597 return std::make_shared<GenericPageTableFault>(vaddr_tainted);
598 req->setPaddr(paddr);
599
600 return finalizePhysical(req, tc, mode);
601}
602
603Fault
604TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
605{
606 // a data cache maintenance instruction that operates by MVA does
607 // not generate a Data Abort exeception due to a Permission fault
608 if (req->isCacheMaintenance()) {
609 return NoFault;
610 }
611
612 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify

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774 ArmFault::PermissionLL + te->lookupLevel,
775 isStage2 | !abt, tranMethod);
776 }
777 return NoFault;
778}
779
780
781Fault
782TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
783 ThreadContext *tc)
784{
785 assert(aarch64);
786
787 // A data cache maintenance instruction that operates by VA does
788 // not generate a Permission fault unless:
789 // * It is a data cache invalidate (dc ivac) which requires write
790 // permissions to the VA, or

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984 isStage2, ArmFault::LpaeTran);
985 }
986 }
987
988 return NoFault;
989}
990
991Fault
992TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
993 Translation *translation, bool &delay, bool timing,
994 TLB::ArmTranslationType tranType, bool functional)
995{
996 // No such thing as a functional timing access
997 assert(!(timing && functional));
998
999 updateMiscReg(tc, tranType);
1000

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1153 // translation has completed (i.e., there is a table entry).
1154 return te ? finalizePhysical(req, tc, mode) : NoFault;
1155 } else {
1156 return fault;
1157 }
1158}
1159
1160Fault
1161TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
1162 TLB::ArmTranslationType tranType)
1163{
1164 updateMiscReg(tc, tranType);
1165
1166 if (directToStage2) {
1167 assert(stage2Tlb);
1168 return stage2Tlb->translateAtomic(req, tc, mode, tranType);
1169 }

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1174 fault = translateFs(req, tc, mode, NULL, delay, false, tranType);
1175 else
1176 fault = translateSe(req, tc, mode, NULL, delay, false);
1177 assert(!delay);
1178 return fault;
1179}
1180
1181Fault
1182TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
1183 TLB::ArmTranslationType tranType)
1184{
1185 updateMiscReg(tc, tranType);
1186
1187 if (directToStage2) {
1188 assert(stage2Tlb);
1189 return stage2Tlb->translateFunctional(req, tc, mode, tranType);
1190 }

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1195 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true);
1196 else
1197 fault = translateSe(req, tc, mode, NULL, delay, false);
1198 assert(!delay);
1199 return fault;
1200}
1201
1202void
1203TLB::translateTiming(RequestPtr req, ThreadContext *tc,
1204 Translation *translation, Mode mode, TLB::ArmTranslationType tranType)
1205{
1206 updateMiscReg(tc, tranType);
1207
1208 if (directToStage2) {
1209 assert(stage2Tlb);
1210 stage2Tlb->translateTiming(req, tc, translation, mode, tranType);
1211 return;
1212 }
1213
1214 assert(translation);
1215
1216 translateComplete(req, tc, translation, mode, tranType, isStage2);
1217}
1218
1219Fault
1220TLB::translateComplete(RequestPtr req, ThreadContext *tc,
1221 Translation *translation, Mode mode, TLB::ArmTranslationType tranType,
1222 bool callFromS2)
1223{
1224 bool delay = false;
1225 Fault fault;
1226 if (FullSystem)
1227 fault = translateFs(req, tc, mode, translation, delay, true, tranType);
1228 else

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1399 return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
1400
1401 default:
1402 panic("Unknown translation mode!\n");
1403 }
1404}
1405
1406Fault
1407TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
1408 Translation *translation, bool timing, bool functional,
1409 bool is_secure, TLB::ArmTranslationType tranType)
1410{
1411 bool is_fetch = (mode == Execute);
1412 bool is_write = (mode == Write);
1413
1414 Addr vaddr_tainted = req->getVaddr();
1415 Addr vaddr = 0;

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1461 writeHits++;
1462 else
1463 readHits++;
1464 }
1465 return NoFault;
1466}
1467
1468Fault
1469TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
1470 Translation *translation, bool timing, bool functional,
1471 TlbEntry *mergeTe)
1472{
1473 Fault fault;
1474
1475 if (isStage2) {
1476 // We are already in the stage 2 TLB. Grab the table entry for stage
1477 // 2 only. We are here because stage 1 translation is disabled.

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1544 } else {
1545 TlbTestInterface *ti(dynamic_cast<TlbTestInterface *>(_ti));
1546 fatal_if(!ti, "%s is not a valid ARM TLB tester\n", _ti->name());
1547 test = ti;
1548 }
1549}
1550
1551Fault
1552TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain)
1553{
1554 if (!test || !req->hasSize() || req->getSize() == 0 ||
1555 req->isCacheMaintenance()) {
1556 return NoFault;
1557 } else {
1558 return test->translationCheck(req, isPriv, mode, domain);
1559 }
1560}

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