1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1215 isSecure = inSecureState(tc) &&
1216 !(tranType & HypMode) && !(tranType & S1S2NsTran);
1217
1218 const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
1219 aarch64 = opModeIs64(op_mode) ||
1220 (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
1221
1222 if (aarch64) { // AArch64
1223 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1224 switch (aarch64EL) {
1225 case EL0:
1226 case EL1:
1227 {
1228 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1229 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);
1230 uint64_t ttbr_asid = ttbcr.a1 ?
1231 tc->readMiscReg(MISCREG_TTBR1_EL1) :

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1253 isHyp = tranType & HypMode;
1254 isHyp &= (tranType & S1S2NsTran) == 0;
1255 isHyp &= (tranType & S1CTran) == 0;
1256 // Work out if we should skip the first stage of translation and go
1257 // directly to stage 2. This value is cached so we don't have to
1258 // compute it for every translation.
1259 stage2Req = isStage2 ||
1260 (hcr.vm && !isHyp && !isSecure &&
1261 !(tranType & S1CTran) && (aarch64EL < EL2));
1262 directToStage2 = !isStage2 && stage2Req && !sctlr.m;
1263 } else {
1264 vmid = 0;
1265 isHyp = false;
1266 directToStage2 = false;
1267 stage2Req = false;
1268 }
1269 } else { // AArch32

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