1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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806 uint8_t pxn = te->pxn;
807 bool r = !is_write && !is_fetch;
808 bool w = is_write;
809 bool x = is_fetch;
810 DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, "
811 "w:%d, x:%d\n", ap, xn, pxn, r, w, x);
812
813 if (isStage2) {
814 panic("Virtualization in AArch64 state is not supported yet");
815 } else {
816 switch (aarch64EL) {
817 case EL0:
818 {
819 uint8_t perm = (ap << 2) | (xn << 1) | pxn;
820 switch (perm) {
821 case 0:
822 case 1:

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1228 asid = -1;
1229 break;
1230 case EL3:
1231 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3);
1232 ttbcr = tc->readMiscReg(MISCREG_TCR_EL3);
1233 asid = -1;
1234 break;
1235 }
1236 scr = tc->readMiscReg(MISCREG_SCR_EL3);
1237 isPriv = aarch64EL != EL0;
1238 // @todo: modify this behaviour to support Virtualization in
1239 // AArch64
1240 vmid = 0;
1241 isHyp = false;
1242 directToStage2 = false;
1243 stage2Req = false;
1244 } else { // AArch32
1245 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
1246 !isSecure));
1247 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc,
1248 !isSecure));
1249 scr = tc->readMiscReg(MISCREG_SCR);
1250 isPriv = cpsr.mode != MODE_USER;
1251 if (longDescFormatInUse(tc)) {

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1357}
1358
1359Fault
1360TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
1361 Translation *translation, bool timing, bool functional,
1362 TlbEntry *mergeTe)
1363{
1364 Fault fault;
1365 TlbEntry *s1Te = NULL;
1366
1367 Addr vaddr_tainted = req->getVaddr();
1368
1369 // Get the stage 1 table entry
1370 fault = getTE(&s1Te, req, tc, mode, translation, timing, functional,
1371 isSecure, curTranType);
1372 // only proceed if we have a valid table entry

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