1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1192 // one type of translation anyway
1193 if (miscRegValid && miscRegContext == tc->contextId() &&
1194 ((tranType == curTranType) || isStage2)) {
1195 return;
1196 }
1197
1198 DPRINTF(TLBVerbose, "TLB variables changed!\n");
1199 cpsr = tc->readMiscReg(MISCREG_CPSR);
1200 // Dependencies: SCR/SCR_EL3, CPSR
1201 isSecure = inSecureState(tc);
1202 isSecure &= (tranType & HypMode) == 0;
1203 isSecure &= (tranType & S1S2NsTran) == 0;
1204 aarch64 = !cpsr.width;
1205 if (aarch64) { // AArch64
1206 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
1207 switch (aarch64EL) {
1208 case EL0:
1209 case EL1:
1210 {
1211 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1212 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);

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