1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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70
71using namespace std;
72using namespace ArmISA;
73
74TLB::TLB(const ArmTLBParams *p)
75 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
76 isStage2(p->is_stage2), stage2Req(false), _attr(0),
77 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
78 stage2Mmu(NULL), rangeMRU(1),
79 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
80 isHyp(false), asid(0), vmid(0), dacr(0),
81 miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
82{
83 tableWalker->setTlb(this);
84
85 // Cache system-level properties
86 haveLPAE = tableWalker->haveLPAE();

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572 if (!p->pTable->translate(vaddr, paddr))
573 return std::make_shared<GenericPageTableFault>(vaddr_tainted);
574 req->setPaddr(paddr);
575
576 return NoFault;
577}
578
579Fault
580TLB::trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain)
581{
582 return NoFault;
583}
584
585Fault
586TLB::walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
587 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)
588{
589 return NoFault;
590}
591
592Fault
593TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
594{
595 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
596 uint32_t flags = req->getFlags();
597 bool is_fetch = (mode == Execute);
598 bool is_write = (mode == Write);
599 bool is_priv = isPriv && !(flags & UserMode);
600

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1033 }
1034 temp_te.setAttributes(long_desc_format);
1035 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
1036 "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
1037 temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
1038 isStage2);
1039 setAttr(temp_te.attributes);
1040
1041 return trickBoxCheck(req, mode, TlbEntry::DomainType::NoAccess);
1042 }
1043
1044 DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n",
1045 isStage2 ? "IPA" : "VA", vaddr_tainted, asid);
1046 // Translation enabled
1047
1048 TlbEntry *te = NULL;
1049 TlbEntry mergeTe;

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1086 return std::make_shared<DataAbort>(
1087 vaddr_tainted,
1088 TlbEntry::DomainType::NoAccess, is_write,
1089 ArmFault::AlignmentFault, isStage2,
1090 tranMethod);
1091 }
1092
1093 // Check for a trickbox generated address fault
1094 if (fault == NoFault) {
1095 fault = trickBoxCheck(req, mode, te->domain);
1096 }
1097 }
1098
1099 // Generate Illegal Inst Set State fault if IL bit is set in CPSR
1100 if (fault == NoFault) {
1101 if (aarch64 && is_fetch && cpsr.il == 1) {
1102 return std::make_shared<IllegalInstSetStateFault>();
1103 }
1104 }

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1414 }
1415 }
1416 *te = s1Te;
1417 }
1418 }
1419 return fault;
1420}
1421
1422ArmISA::TLB *
1423ArmTLBParams::create()
1424{
1425 return new ArmISA::TLB(this);
1426}