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1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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192
193 //inserting to MRU position and evicting the LRU one
194
195 for (int i = size - 1; i > 0; --i)
196 table[i] = table[i-1];
197 table[0] = entry;
198
199 inserts++;
200}
201
202void
203TLB::printTlb() const
204{
205 int x = 0;
206 TlbEntry *te;
207 DPRINTF(TLB, "Current TLB contents:\n");

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526 instAccesses = instHits + instMisses;
527 readAccesses = readHits + readMisses;
528 writeAccesses = writeHits + writeMisses;
529 hits = readHits + writeHits + instHits;
530 misses = readMisses + writeMisses + instMisses;
531 accesses = readAccesses + writeAccesses + instAccesses;
532}
533
534Fault
535TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
536 Translation *translation, bool &delay, bool timing)
537{
538 updateMiscReg(tc);
539 Addr vaddr_tainted = req->getVaddr();
540 Addr vaddr = 0;
541 if (aarch64)

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