table_walker.hh (8832:247fee427324) table_walker.hh (8851:7e966326ef5b)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include <list>
44
45#include "arch/arm/miscregs.hh"
46#include "arch/arm/tlb.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include <list>
44
45#include "arch/arm/miscregs.hh"
46#include "arch/arm/tlb.hh"
47#include "dev/io_device.hh"
47#include "mem/mem_object.hh"
48#include "mem/request.hh"
49#include "params/ArmTableWalker.hh"
50#include "sim/eventq.hh"
51#include "sim/fault_fwd.hh"
52
53class DmaPort;
54class ThreadContext;

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323 std::list<WalkerState *> stateQueueL2;
324
325 /** Queue of requests that have passed are waiting because the walker is
326 * currently busy. */
327 std::list<WalkerState *> pendingQueue;;
328
329
330 /** Port to issue translation requests from */
48#include "mem/mem_object.hh"
49#include "mem/request.hh"
50#include "params/ArmTableWalker.hh"
51#include "sim/eventq.hh"
52#include "sim/fault_fwd.hh"
53
54class DmaPort;
55class ThreadContext;

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324 std::list<WalkerState *> stateQueueL2;
325
326 /** Queue of requests that have passed are waiting because the walker is
327 * currently busy. */
328 std::list<WalkerState *> pendingQueue;;
329
330
331 /** Port to issue translation requests from */
331 DmaPort *port;
332 DmaPort port;
332
333 /** TLB that is initiating these table walks */
334 TLB *tlb;
335
336 /** Cached copy of the sctlr as it existed when translation began */
337 SCTLR sctlr;
338
339 WalkerState *currState;

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334 /** TLB that is initiating these table walks */
335 TLB *tlb;
336
337 /** Cached copy of the sctlr as it existed when translation began */
338 SCTLR sctlr;
339
340 WalkerState *currState;

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