table_walker.hh (7878:d3e6ebcccabf) table_walker.hh (7946:7c58c106d28d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 return bits(data, 18);
89 }
90
91 /** Return the physcal address of the entry, bits in position*/
92 Addr paddr() const
93 {
94 if (supersection())
95 panic("Super sections not implemented\n");
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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88 return bits(data, 18);
89 }
90
91 /** Return the physcal address of the entry, bits in position*/
92 Addr paddr() const
93 {
94 if (supersection())
95 panic("Super sections not implemented\n");
96 return mbits(data, 31,20);
96 return mbits(data, 31, 20);
97 }
98 /** Return the physcal address of the entry, bits in position*/
99 Addr paddr(Addr va) const
100 {
101 if (supersection())
102 panic("Super sections not implemented\n");
97 }
98 /** Return the physcal address of the entry, bits in position*/
99 Addr paddr(Addr va) const
100 {
101 if (supersection())
102 panic("Super sections not implemented\n");
103 return mbits(data, 31,20) | mbits(va, 20, 0);
103 return mbits(data, 31, 20) | mbits(va, 19, 0);
104 }
105
106
107 /** Return the physical frame, bits shifted right */
108 Addr pfn() const
109 {
110 if (supersection())
111 panic("Super sections not implemented\n");
104 }
105
106
107 /** Return the physical frame, bits shifted right */
108 Addr pfn() const
109 {
110 if (supersection())
111 panic("Super sections not implemented\n");
112 return bits(data, 31,20);
112 return bits(data, 31, 20);
113 }
114
115 /** Is the translation global (no asid used)? */
116 bool global() const
117 {
118 return bits(data, 17);
119 }
120
121 /** Is the translation not allow execution? */
122 bool xn() const
123 {
124 return bits(data, 4);
125 }
126
127 /** Three bit access protection flags */
128 uint8_t ap() const
129 {
113 }
114
115 /** Is the translation global (no asid used)? */
116 bool global() const
117 {
118 return bits(data, 17);
119 }
120
121 /** Is the translation not allow execution? */
122 bool xn() const
123 {
124 return bits(data, 4);
125 }
126
127 /** Three bit access protection flags */
128 uint8_t ap() const
129 {
130 return (bits(data, 15) << 2) | bits(data,11,10);
130 return (bits(data, 15) << 2) | bits(data, 11, 10);
131 }
132
133 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
134 uint8_t domain() const
135 {
131 }
132
133 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
134 uint8_t domain() const
135 {
136 return bits(data,8,5);
136 return bits(data, 8, 5);
137 }
138
139 /** Address of L2 descriptor if it exists */
140 Addr l2Addr() const
141 {
137 }
138
139 /** Address of L2 descriptor if it exists */
140 Addr l2Addr() const
141 {
142 return mbits(data, 31,10);
142 return mbits(data, 31, 10);
143 }
144
145 /** Memory region attributes: ARM DDI 0406B: B3-32.
146 * These bits are largly ignored by M5 and only used to
147 * provide the illusion that the memory system cares about
148 * anything but cachable vs. uncachable.
149 */
150 uint8_t texcb() const
151 {
143 }
144
145 /** Memory region attributes: ARM DDI 0406B: B3-32.
146 * These bits are largly ignored by M5 and only used to
147 * provide the illusion that the memory system cares about
148 * anything but cachable vs. uncachable.
149 */
150 uint8_t texcb() const
151 {
152 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
152 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
153 }
154
155 /** If the section is shareable. See texcb() comment. */
156 bool shareable() const
157 {
158 return bits(data, 16);
159 }
160

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182
183 /** This entry has been modified (access flag set) and needs to be
184 * written back to memory */
185 bool _dirty;
186
187 /** Is the entry invalid */
188 bool invalid() const
189 {
153 }
154
155 /** If the section is shareable. See texcb() comment. */
156 bool shareable() const
157 {
158 return bits(data, 16);
159 }
160

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182
183 /** This entry has been modified (access flag set) and needs to be
184 * written back to memory */
185 bool _dirty;
186
187 /** Is the entry invalid */
188 bool invalid() const
189 {
190 return bits(data, 1,0) == 0;;
190 return bits(data, 1, 0) == 0;
191 }
192
193 /** What is the size of the mapping? */
194 bool large() const
195 {
196 return bits(data, 1) == 0;
197 }
198

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213 {
214 return bits(data, 5, 4) | (bits(data, 9) << 2);
215 }
216
217 /** Memory region attributes: ARM DDI 0406B: B3-32 */
218 uint8_t texcb() const
219 {
220 return large() ?
191 }
192
193 /** What is the size of the mapping? */
194 bool large() const
195 {
196 return bits(data, 1) == 0;
197 }
198

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213 {
214 return bits(data, 5, 4) | (bits(data, 9) << 2);
215 }
216
217 /** Memory region attributes: ARM DDI 0406B: B3-32 */
218 uint8_t texcb() const
219 {
220 return large() ?
221 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
222 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
222 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
223 }
224
225 /** Return the physical frame, bits shifted right */
226 Addr pfn() const
227 {
228 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
229 }
230

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224
225 /** Return the physical frame, bits shifted right */
226 Addr pfn() const
227 {
228 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
229 }
230

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