table_walker.hh (7678:f19b6a3a8cec) table_walker.hh (7694:de057cccee82)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55class ThreadContext;
56
57namespace ArmISA {
58class Translation;
59class TLB;
60
61class TableWalker : public MemObject
62{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55class ThreadContext;
56
57namespace ArmISA {
58class Translation;
59class TLB;
60
61class TableWalker : public MemObject
62{
63 protected:
63 public:
64 struct L1Descriptor {
65 /** Type of page table entry ARM DDI 0406B: B3-8*/
66 enum EntryType {
67 Ignore,
68 PageTable,
69 Section,
70 Reserved
71 };

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90
91 /** Return the physcal address of the entry, bits in position*/
92 Addr paddr() const
93 {
94 if (supersection())
95 panic("Super sections not implemented\n");
96 return mbits(data, 31,20);
97 }
64 struct L1Descriptor {
65 /** Type of page table entry ARM DDI 0406B: B3-8*/
66 enum EntryType {
67 Ignore,
68 PageTable,
69 Section,
70 Reserved
71 };

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90
91 /** Return the physcal address of the entry, bits in position*/
92 Addr paddr() const
93 {
94 if (supersection())
95 panic("Super sections not implemented\n");
96 return mbits(data, 31,20);
97 }
98 /** Return the physcal address of the entry, bits in position*/
99 Addr paddr(Addr va) const
100 {
101 if (supersection())
102 panic("Super sections not implemented\n");
103 return mbits(data, 31,20) | mbits(va, 20, 0);
104 }
98
105
106
99 /** Return the physical frame, bits shifted right */
100 Addr pfn() const
101 {
102 if (supersection())
103 panic("Super sections not implemented\n");
104 return bits(data, 31,20);
105 }
106

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215 }
216
217 /** Return the physical frame, bits shifted right */
218 Addr pfn() const
219 {
220 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
221 }
222
107 /** Return the physical frame, bits shifted right */
108 Addr pfn() const
109 {
110 if (supersection())
111 panic("Super sections not implemented\n");
112 return bits(data, 31,20);
113 }
114

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223 }
224
225 /** Return the physical frame, bits shifted right */
226 Addr pfn() const
227 {
228 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
229 }
230
231 /** Return complete physical address given a VA */
232 Addr paddr(Addr va) const
233 {
234 if (large())
235 return mbits(data, 31, 16) | mbits(va, 15, 0);
236 else
237 return mbits(data, 31, 12) | mbits(va, 11, 0);
238 }
239
223 /** If the section is shareable. See texcb() comment. */
224 bool shareable() const
225 {
226 return bits(data, 10);
227 }
228
229 /** Set access flag that this entry has been touched. Mark
230 * the entry as requiring a writeback, in the future.

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261 Fault fault;
262
263 /** The virtual address that is being translated */
264 Addr vaddr;
265
266 /** Cached copy of the sctlr as it existed when translation began */
267 SCTLR sctlr;
268
240 /** If the section is shareable. See texcb() comment. */
241 bool shareable() const
242 {
243 return bits(data, 10);
244 }
245
246 /** Set access flag that this entry has been touched. Mark
247 * the entry as requiring a writeback, in the future.

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278 Fault fault;
279
280 /** The virtual address that is being translated */
281 Addr vaddr;
282
283 /** Cached copy of the sctlr as it existed when translation began */
284 SCTLR sctlr;
285
269 /** Cached copy of the cpsr as it existed when the translation began */
270 CPSR cpsr;
271
272 /** Width of the base address held in TTRB0 */
273 uint32_t N;
274
275 /** If the access is a write */
276 bool isWrite;
277
286 /** Width of the base address held in TTRB0 */
287 uint32_t N;
288
289 /** If the access is a write */
290 bool isWrite;
291
278 /** If the access is not from user mode */
279 bool isPriv;
280
281 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
282 bool isFetch;
283
284 /** If the mode is timing or atomic */
285 bool timing;
286
287 /** Save mode for use in delayed response */
288 BaseTLB::Mode mode;

--- 73 unchanged lines hidden --- 		292 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
293 bool isFetch;
294
295 /** If the mode is timing or atomic */
296 bool timing;
297
298 /** Save mode for use in delayed response */
299 BaseTLB::Mode mode;

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