table_walker.hh (7406:ddc26bd4ea7d) table_walker.hh (7436:b578349f9371)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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63 /** Type of page table entry ARM DDI 0406B: B3-8*/
64 enum EntryType {
65 Ignore,
66 PageTable,
67 Section,
68 Reserved
69 };
70
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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63 /** Type of page table entry ARM DDI 0406B: B3-8*/
64 enum EntryType {
65 Ignore,
66 PageTable,
67 Section,
68 Reserved
69 };
70
71 /** The raw bits of the entry */
71 uint32_t data;
72
72 uint32_t data;
73
74 /** This entry has been modified (access flag set) and needs to be
75 * written back to memory */
76 bool _dirty;
77
73 EntryType type() const
74 {
75 return (EntryType)(data & 0x3);
76 }
77
78 /** Is the page a Supersection (16MB)?*/
79 bool supersection() const
80 {

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122 }
123
124 /** Address of L2 descriptor if it exists */
125 Addr l2Addr() const
126 {
127 return mbits(data, 31,10);
128 }
129
78 EntryType type() const
79 {
80 return (EntryType)(data & 0x3);
81 }
82
83 /** Is the page a Supersection (16MB)?*/
84 bool supersection() const
85 {

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127 }
128
129 /** Address of L2 descriptor if it exists */
130 Addr l2Addr() const
131 {
132 return mbits(data, 31,10);
133 }
134
130 /** Memory region attributes: ARM DDI 0406B: B3-32 */
135 /** Memory region attributes: ARM DDI 0406B: B3-32.
136 * These bits are largly ignored by M5 and only used to
137 * provide the illusion that the memory system cares about
138 * anything but cachable vs. uncachable.
139 */
131 uint8_t texcb() const
132 {
133 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
134 }
135
140 uint8_t texcb() const
141 {
142 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
143 }
144
145 /** If the section is shareable. See texcb() comment. */
146 bool shareable() const
147 {
148 return bits(data, 16);
149 }
150
151 /** Set access flag that this entry has been touched. Mark
152 * the entry as requiring a writeback, in the future.
153 */
154 void setAp0()
155 {
156 data |= 1 << 10;
157 _dirty = true;
158 }
159
160 /** This entry needs to be written back to memory */
161 bool dirty() const
162 {
163 return _dirty;
164 }
136 };
137
138 /** Level 2 page table descriptor */
139 struct L2Descriptor {
140
165 };
166
167 /** Level 2 page table descriptor */
168 struct L2Descriptor {
169
170 /** The raw bits of the entry. */
141 uint32_t data;
142
171 uint32_t data;
172
173 /** This entry has been modified (access flag set) and needs to be
174 * written back to memory */
175 bool _dirty;
176
143 /** Is the entry invalid */
144 bool invalid() const
145 {
146 return bits(data, 1,0) == 0;;
147 }
148
149 /** What is the size of the mapping? */
150 bool large() const

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179 }
180
181 /** Return the physical frame, bits shifted right */
182 Addr pfn() const
183 {
184 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
185 }
186
177 /** Is the entry invalid */
178 bool invalid() const
179 {
180 return bits(data, 1,0) == 0;;
181 }
182
183 /** What is the size of the mapping? */
184 bool large() const

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213 }
214
215 /** Return the physical frame, bits shifted right */
216 Addr pfn() const
217 {
218 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
219 }
220
221 /** If the section is shareable. See texcb() comment. */
222 bool shareable() const
223 {
224 return bits(data, 10);
225 }
226
227 /** Set access flag that this entry has been touched. Mark
228 * the entry as requiring a writeback, in the future.
229 */
230 void setAp0()
231 {
232 data |= 1 << 4;
233 _dirty = true;
234 }
235
236 /** This entry needs to be written back to memory */
237 bool dirty() const
238 {
239 return _dirty;
240 }
241
187 };
188
189 /** Port to issue translation requests from */
190 DmaPort *port;
191
192 /** TLB that is initiating these table walks */
193 TLB *tlb;
194

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247
248 virtual unsigned int drain(Event *de) { panic("write me\n"); }
249 virtual Port *getPort(const std::string &if_name, int idx = -1);
250
251 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
252 TLB::Translation *_trans, bool timing);
253
254 void setTlb(TLB *_tlb) { tlb = _tlb; }
242 };
243
244 /** Port to issue translation requests from */
245 DmaPort *port;
246
247 /** TLB that is initiating these table walks */
248 TLB *tlb;
249

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302
303 virtual unsigned int drain(Event *de) { panic("write me\n"); }
304 virtual Port *getPort(const std::string &if_name, int idx = -1);
305
306 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
307 TLB::Translation *_trans, bool timing);
308
309 void setTlb(TLB *_tlb) { tlb = _tlb; }
310 void memAttrs(TlbEntry &te, uint8_t texcb, bool s);
255
256 private:
311
312 private:
257 void memAttrs(TlbEntry &te, uint8_t texcb);
258
259 void doL1Descriptor();
260 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent;
261
262 void doL2Descriptor();
263 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent;
264
265
266};
267
268
269} // namespace ArmISA
270
271#endif //__ARCH_ARM_TABLE_WALKER_HH__
272
313
314 void doL1Descriptor();
315 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent;
316
317 void doL2Descriptor();
318 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent;
319
320
321};
322
323
324} // namespace ArmISA
325
326#endif //__ARCH_ARM_TABLE_WALKER_HH__
327