table_walker.hh (10621:b7bc5b1084a4) table_walker.hh (10717:4f8c1bd6fdb8)
1/*
1/*
2 * Copyright (c) 2010-2014 ARM Limited
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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42#define __ARCH_ARM_TABLE_WALKER_HH__
43
44#include <list>
45
46#include "arch/arm/miscregs.hh"
47#include "arch/arm/system.hh"
48#include "arch/arm/tlb.hh"
49#include "dev/dma_device.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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42#define __ARCH_ARM_TABLE_WALKER_HH__
43
44#include <list>
45
46#include "arch/arm/miscregs.hh"
47#include "arch/arm/system.hh"
48#include "arch/arm/tlb.hh"
49#include "dev/dma_device.hh"
50#include "mem/mem_object.hh"
51#include "mem/request.hh"
52#include "params/ArmTableWalker.hh"
53#include "sim/eventq.hh"
54
55class ThreadContext;
56
57namespace ArmISA {
58class Translation;

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807
808 WalkerState();
809
810 std::string name() const { return tableWalker->name(); }
811 };
812
813 protected:
814
50#include "mem/request.hh"
51#include "params/ArmTableWalker.hh"
52#include "sim/eventq.hh"
53
54class ThreadContext;
55
56namespace ArmISA {
57class Translation;

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806
807 WalkerState();
808
809 std::string name() const { return tableWalker->name(); }
810 };
811
812 protected:
813
815 /**
816 * A snooping DMA port that currently does nothing besides
817 * extending the DMA port to accept snoops without complaining.
818 */
819 class SnoopingDmaPort : public DmaPort
820 {
821
822 protected:
823
824 virtual void recvTimingSnoopReq(PacketPtr pkt)
825 { }
826
827 virtual Tick recvAtomicSnoop(PacketPtr pkt)
828 { return 0; }
829
830 virtual void recvFunctionalSnoop(PacketPtr pkt)
831 { }
832
833 virtual bool isSnooping() const { return true; }
834
835 public:
836
837 /**
838 * A snooping DMA port merely calls the construtor of the DMA
839 * port.
840 */
841 SnoopingDmaPort(MemObject *dev, System *s) :
842 DmaPort(dev, s)
843 { }
844 };
845
846 /** Queues of requests for all the different lookup levels */
847 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
848
849 /** Queue of requests that have passed are waiting because the walker is
850 * currently busy. */
851 std::list<WalkerState *> pendingQueue;
852
814 /** Queues of requests for all the different lookup levels */
815 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
816
817 /** Queue of requests that have passed are waiting because the walker is
818 * currently busy. */
819 std::list<WalkerState *> pendingQueue;
820
853
854 /** Port to issue translation requests from */
855 SnoopingDmaPort port;
856
857 /** If we're draining keep the drain event around until we're drained */
858 DrainManager *drainManager;
859
860 /** The MMU to forward second stage look upts to */
861 Stage2MMU *stage2Mmu;
862
821 /** If we're draining keep the drain event around until we're drained */
822 DrainManager *drainManager;
823
824 /** The MMU to forward second stage look upts to */
825 Stage2MMU *stage2Mmu;
826
827 /** Port shared by the two table walkers. */
828 DmaPort* port;
829
830 /** Master id assigned by the MMU. */
831 MasterID masterId;
832
863 /** Indicates whether this table walker is part of the stage 2 mmu */
864 const bool isStage2;
865
866 /** TLB that is initiating these table walks */
867 TLB *tlb;
868
869 /** Cached copy of the sctlr as it existed when translation began */
870 SCTLR sctlr;
871
872 WalkerState *currState;
873
874 /** If a timing translation is currently in progress */
875 bool pending;
876
833 /** Indicates whether this table walker is part of the stage 2 mmu */
834 const bool isStage2;
835
836 /** TLB that is initiating these table walks */
837 TLB *tlb;
838
839 /** Cached copy of the sctlr as it existed when translation began */
840 SCTLR sctlr;
841
842 WalkerState *currState;
843
844 /** If a timing translation is currently in progress */
845 bool pending;
846
877 /** Request id for requests generated by this walker */
878 MasterID masterId;
879
880 /** The number of walks belonging to squashed instructions that can be
881 * removed from the pendingQueue per cycle. */
882 unsigned numSquashable;
883
884 /** Cached copies of system-level properties */
885 bool haveSecurity;
886 bool _haveLPAE;
887 bool _haveVirtualization;
888 uint8_t physAddrRange;
889 bool _haveLargeAsid64;
847 /** The number of walks belonging to squashed instructions that can be
848 * removed from the pendingQueue per cycle. */
849 unsigned numSquashable;
850
851 /** Cached copies of system-level properties */
852 bool haveSecurity;
853 bool _haveLPAE;
854 bool _haveVirtualization;
855 uint8_t physAddrRange;
856 bool _haveLargeAsid64;
890 ArmSystem *armSys;
891
892 /** Statistics */
893 Stats::Scalar statWalks;
894 Stats::Scalar statWalksShortDescriptor;
895 Stats::Scalar statWalksLongDescriptor;
896 Stats::Vector statWalksShortTerminatedAtLevel;
897 Stats::Vector statWalksLongTerminatedAtLevel;
898 Stats::Scalar statSquashedBefore;

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915 virtual ~TableWalker();
916
917 const Params *
918 params() const
919 {
920 return dynamic_cast<const Params *>(_params);
921 }
922
857
858 /** Statistics */
859 Stats::Scalar statWalks;
860 Stats::Scalar statWalksShortDescriptor;
861 Stats::Scalar statWalksLongDescriptor;
862 Stats::Vector statWalksShortTerminatedAtLevel;
863 Stats::Vector statWalksLongTerminatedAtLevel;
864 Stats::Scalar statSquashedBefore;

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881 virtual ~TableWalker();
882
883 const Params *
884 params() const
885 {
886 return dynamic_cast<const Params *>(_params);
887 }
888
889 virtual void init();
890
923 bool haveLPAE() const { return _haveLPAE; }
924 bool haveVirtualization() const { return _haveVirtualization; }
925 bool haveLargeAsid64() const { return _haveLargeAsid64; }
926 /** Checks if all state is cleared and if so, completes drain */
927 void completeDrain();
928 unsigned int drain(DrainManager *dm);
929 virtual void drainResume();
891 bool haveLPAE() const { return _haveLPAE; }
892 bool haveVirtualization() const { return _haveVirtualization; }
893 bool haveLargeAsid64() const { return _haveLargeAsid64; }
894 /** Checks if all state is cleared and if so, completes drain */
895 void completeDrain();
896 unsigned int drain(DrainManager *dm);
897 virtual void drainResume();
898
930 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
931 PortID idx = InvalidPortID);
899 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
900 PortID idx = InvalidPortID);
901
932 void regStats();
933
902 void regStats();
903
934 /**
935 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
936 * access the table walker port through the TLB so that it can
937 * orchestrate staged translations.
938 *
939 * @return Our DMA port
940 */
941 DmaPort& getWalkerPort() { return port; }
942
943 Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
944 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
945 bool timing, bool functional, bool secure,
946 TLB::ArmTranslationType tranType);
947
948 void setTlb(TLB *_tlb) { tlb = _tlb; }
949 TLB* getTlb() { return tlb; }
904 Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
905 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
906 bool timing, bool functional, bool secure,
907 TLB::ArmTranslationType tranType);
908
909 void setTlb(TLB *_tlb) { tlb = _tlb; }
910 TLB* getTlb() { return tlb; }
950 void setMMU(Stage2MMU *m) { stage2Mmu = m; }
911 void setMMU(Stage2MMU *m, MasterID master_id);
951 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
952 uint8_t texcb, bool s);
953 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
954 LongDescriptor &lDescriptor);
955 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx,
956 uint8_t sh);
957
958 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);

--- 57 unchanged lines hidden --- 		912 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
913 uint8_t texcb, bool s);
914 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
915 LongDescriptor &lDescriptor);
916 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx,
917 uint8_t sh);
918
919 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);

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