table_walker.hh (10537:47fe87b0cf97) table_walker.hh (10621:b7bc5b1084a4)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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789 LongDescriptor longDesc;
790
791 /** Whether the response is delayed in timing mode due to additional
792 * lookups */
793 bool delayed;
794
795 TableWalker *tableWalker;
796
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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789 LongDescriptor longDesc;
790
791 /** Whether the response is delayed in timing mode due to additional
792 * lookups */
793 bool delayed;
794
795 TableWalker *tableWalker;
796
797 /** Timestamp for calculating elapsed time in service (for stats) */
798 Tick startTime;
799
800 /** Page entries walked during service (for stats) */
801 unsigned levels;
802
797 void doL1Descriptor();
798 void doL2Descriptor();
799
800 void doLongDescriptor();
801
802 WalkerState();
803
804 std::string name() const { return tableWalker->name(); }

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878 /** Cached copies of system-level properties */
879 bool haveSecurity;
880 bool _haveLPAE;
881 bool _haveVirtualization;
882 uint8_t physAddrRange;
883 bool _haveLargeAsid64;
884 ArmSystem *armSys;
885
803 void doL1Descriptor();
804 void doL2Descriptor();
805
806 void doLongDescriptor();
807
808 WalkerState();
809
810 std::string name() const { return tableWalker->name(); }

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884 /** Cached copies of system-level properties */
885 bool haveSecurity;
886 bool _haveLPAE;
887 bool _haveVirtualization;
888 uint8_t physAddrRange;
889 bool _haveLargeAsid64;
890 ArmSystem *armSys;
891
892 /** Statistics */
893 Stats::Scalar statWalks;
894 Stats::Scalar statWalksShortDescriptor;
895 Stats::Scalar statWalksLongDescriptor;
896 Stats::Vector statWalksShortTerminatedAtLevel;
897 Stats::Vector statWalksLongTerminatedAtLevel;
898 Stats::Scalar statSquashedBefore;
899 Stats::Scalar statSquashedAfter;
900 Stats::Histogram statWalkWaitTime;
901 Stats::Histogram statWalkServiceTime;
902 Stats::Histogram statPendingWalks; // essentially "L" of queueing theory
903 Stats::Vector statPageSizes;
904 Stats::Vector2d statRequestOrigin;
905
906 mutable unsigned pendingReqs;
907 mutable Tick pendingChangeTick;
908
909 static const unsigned REQUESTED = 0;
910 static const unsigned COMPLETED = 1;
911
886 public:
887 typedef ArmTableWalkerParams Params;
888 TableWalker(const Params *p);
889 virtual ~TableWalker();
890
891 const Params *
892 params() const
893 {

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898 bool haveVirtualization() const { return _haveVirtualization; }
899 bool haveLargeAsid64() const { return _haveLargeAsid64; }
900 /** Checks if all state is cleared and if so, completes drain */
901 void completeDrain();
902 unsigned int drain(DrainManager *dm);
903 virtual void drainResume();
904 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
905 PortID idx = InvalidPortID);
912 public:
913 typedef ArmTableWalkerParams Params;
914 TableWalker(const Params *p);
915 virtual ~TableWalker();
916
917 const Params *
918 params() const
919 {

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924 bool haveVirtualization() const { return _haveVirtualization; }
925 bool haveLargeAsid64() const { return _haveLargeAsid64; }
926 /** Checks if all state is cleared and if so, completes drain */
927 void completeDrain();
928 unsigned int drain(DrainManager *dm);
929 virtual void drainResume();
930 virtual BaseMasterPort& getMasterPort(const std::string &if_name,
931 PortID idx = InvalidPortID);
932 void regStats();
906
907 /**
908 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
909 * access the table walker port through the TLB so that it can
910 * orchestrate staged translations.
911 *
912 * @return Our DMA port
913 */

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971 /// Returns true if the address exceeds the range permitted by the
972 /// system-wide setting or by the TCR_ELx IPS/PS setting
973 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange);
974 Fault processWalkAArch64();
975 void processWalkWrapper();
976 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
977
978 void nextWalk(ThreadContext *tc);
933
934 /**
935 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
936 * access the table walker port through the TLB so that it can
937 * orchestrate staged translations.
938 *
939 * @return Our DMA port
940 */

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998 /// Returns true if the address exceeds the range permitted by the
999 /// system-wide setting or by the TCR_ELx IPS/PS setting
1000 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange);
1001 Fault processWalkAArch64();
1002 void processWalkWrapper();
1003 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
1004
1005 void nextWalk(ThreadContext *tc);
1006
1007 void pendingChange();
1008
1009 static uint8_t pageSizeNtoStatBin(uint8_t N);
979};
980
981} // namespace ArmISA
982
983#endif //__ARCH_ARM_TABLE_WALKER_HH__
984
1010};
1011
1012} // namespace ArmISA
1013
1014#endif //__ARCH_ARM_TABLE_WALKER_HH__
1015