1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63 /** Type of page table entry ARM DDI 0406B: B3-8*/ 64 enum EntryType { 65 Ignore, 66 PageTable, 67 Section, 68 Reserved 69 }; 70 |
71 /** The raw bits of the entry */ |
72 uint32_t data; 73 |
74 /** This entry has been modified (access flag set) and needs to be 75 * written back to memory */ 76 bool _dirty; 77 |
78 EntryType type() const 79 { 80 return (EntryType)(data & 0x3); 81 } 82 83 /** Is the page a Supersection (16MB)?*/ 84 bool supersection() const 85 { --- 41 unchanged lines hidden (view full) --- 127 } 128 129 /** Address of L2 descriptor if it exists */ 130 Addr l2Addr() const 131 { 132 return mbits(data, 31,10); 133 } 134 |
135 /** Memory region attributes: ARM DDI 0406B: B3-32. 136 * These bits are largly ignored by M5 and only used to 137 * provide the illusion that the memory system cares about 138 * anything but cachable vs. uncachable. 139 */ |
140 uint8_t texcb() const 141 { 142 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; 143 } 144 |
145 /** If the section is shareable. See texcb() comment. */ 146 bool shareable() const 147 { 148 return bits(data, 16); 149 } 150 151 /** Set access flag that this entry has been touched. Mark 152 * the entry as requiring a writeback, in the future. 153 */ 154 void setAp0() 155 { 156 data |= 1 << 10; 157 _dirty = true; 158 } 159 160 /** This entry needs to be written back to memory */ 161 bool dirty() const 162 { 163 return _dirty; 164 } |
165 }; 166 167 /** Level 2 page table descriptor */ 168 struct L2Descriptor { 169 |
170 /** The raw bits of the entry. */ |
171 uint32_t data; 172 |
173 /** This entry has been modified (access flag set) and needs to be 174 * written back to memory */ 175 bool _dirty; 176 |
177 /** Is the entry invalid */ 178 bool invalid() const 179 { 180 return bits(data, 1,0) == 0;; 181 } 182 183 /** What is the size of the mapping? */ 184 bool large() const --- 28 unchanged lines hidden (view full) --- 213 } 214 215 /** Return the physical frame, bits shifted right */ 216 Addr pfn() const 217 { 218 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 219 } 220 |
221 /** If the section is shareable. See texcb() comment. */ 222 bool shareable() const 223 { 224 return bits(data, 10); 225 } 226 227 /** Set access flag that this entry has been touched. Mark 228 * the entry as requiring a writeback, in the future. 229 */ 230 void setAp0() 231 { 232 data |= 1 << 4; 233 _dirty = true; 234 } 235 236 /** This entry needs to be written back to memory */ 237 bool dirty() const 238 { 239 return _dirty; 240 } 241 |
242 }; 243 244 /** Port to issue translation requests from */ 245 DmaPort *port; 246 247 /** TLB that is initiating these table walks */ 248 TLB *tlb; 249 --- 52 unchanged lines hidden (view full) --- 302 303 virtual unsigned int drain(Event *de) { panic("write me\n"); } 304 virtual Port *getPort(const std::string &if_name, int idx = -1); 305 306 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 307 TLB::Translation *_trans, bool timing); 308 309 void setTlb(TLB *_tlb) { tlb = _tlb; } |
310 void memAttrs(TlbEntry &te, uint8_t texcb, bool s); |
311 312 private: |
313 314 void doL1Descriptor(); 315 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent; 316 317 void doL2Descriptor(); 318 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent; 319 320 321}; 322 323 324} // namespace ArmISA 325 326#endif //__ARCH_ARM_TABLE_WALKER_HH__ 327 |