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> #include "base/fifo_buffer.hh"
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< /** Port to issue translation requests from */
< DmaPort *port;
---
> struct WalkerState //: public SimObject
> {
> /** Thread context that we're doing the walk for */
> ThreadContext *tc;
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< /** TLB that is initiating these table walks */
< TLB *tlb;
---
> /** Request that is currently being serviced */
> RequestPtr req;
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< /** Thread context that we're doing the walk for */
< ThreadContext *tc;
---
> /** Context ID that we're servicing the request under */
> uint8_t contextId;
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< /** Request that is currently being serviced */
< RequestPtr req;
---
> /** Translation state for delayed requests */
> TLB::Translation *transState;
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< /** Context ID that we're servicing the request under */
< uint8_t contextId;
---
> /** The fault that we are going to return */
> Fault fault;
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< /** Translation state for delayed requests */
< TLB::Translation *transState;
---
> /** The virtual address that is being translated */
> Addr vaddr;
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< /** The fault that we are going to return */
< Fault fault;
---
> /** Cached copy of the sctlr as it existed when translation began */
> SCTLR sctlr;
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< /** The virtual address that is being translated */
< Addr vaddr;
---
> /** Cached copy of the cpsr as it existed when the translation began */
> CPSR cpsr;
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< /** Cached copy of the sctlr as it existed when translation began */
< SCTLR sctlr;
---
> /** Width of the base address held in TTRB0 */
> uint32_t N;
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< /** Cached copy of the cpsr as it existed when the translation began */
< CPSR cpsr;
---
> /** If the access is a write */
> bool isWrite;
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< /** Width of the base address held in TTRB0 */
< uint32_t N;
---
> /** If the access is not from user mode */
> bool isPriv;
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< /** If the access is a write */
< bool isWrite;
---
> /** If the access is a fetch (for execution, and no-exec) must be checked?*/
> bool isFetch;
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< /** If the access is not from user mode */
< bool isPriv;
---
> /** If the mode is timing or atomic */
> bool timing;
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< /** If the access is a fetch (for execution, and no-exec) must be checked?*/
< bool isFetch;
---
> /** Save mode for use in delayed response */
> BaseTLB::Mode mode;
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< /** If the mode is timing or atomic */
< bool timing;
---
> L1Descriptor l1Desc;
> L2Descriptor l2Desc;
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< L1Descriptor l1Desc;
< L2Descriptor l2Desc;
---
> /** Whether L1/L2 descriptor response is delayed in timing mode */
> bool delayed;
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< /** Save mode for use in delayed response */
< BaseTLB::Mode mode;
---
> TableWalker *tableWalker;
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< /** Whether L1/L2 descriptor response is delayed in timing mode */
< bool delayed;
---
> void doL1Descriptor();
> void doL2Descriptor();
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> std::string name() const {return tableWalker->name();}
> };
>
>
> FifoBuffer<WalkerState> stateQueue;
>
> /** Port to issue translation requests from */
> DmaPort *port;
>
> /** TLB that is initiating these table walks */
> TLB *tlb;
>
> /** Cached copy of the sctlr as it existed when translation began */
> SCTLR sctlr;
>
> WalkerState *currState;
>
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< void memAttrs(ThreadContext *tc, TlbEntry &te, uint8_t texcb, bool s);
---
> void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
> uint8_t texcb, bool s);