70a71
> /** The raw bits of the entry */
72a74,77
> /** This entry has been modified (access flag set) and needs to be
> * written back to memory */
> bool _dirty;
>
130c135,139
< /** Memory region attributes: ARM DDI 0406B: B3-32 */
---
> /** Memory region attributes: ARM DDI 0406B: B3-32.
> * These bits are largly ignored by M5 and only used to
> * provide the illusion that the memory system cares about
> * anything but cachable vs. uncachable.
> */
135a145,164
> /** If the section is shareable. See texcb() comment. */
> bool shareable() const
> {
> return bits(data, 16);
> }
>
> /** Set access flag that this entry has been touched. Mark
> * the entry as requiring a writeback, in the future.
> */
> void setAp0()
> {
> data |= 1 << 10;
> _dirty = true;
> }
>
> /** This entry needs to be written back to memory */
> bool dirty() const
> {
> return _dirty;
> }
140a170
> /** The raw bits of the entry. */
142a173,176
> /** This entry has been modified (access flag set) and needs to be
> * written back to memory */
> bool _dirty;
>
186a221,241
> /** If the section is shareable. See texcb() comment. */
> bool shareable() const
> {
> return bits(data, 10);
> }
>
> /** Set access flag that this entry has been touched. Mark
> * the entry as requiring a writeback, in the future.
> */
> void setAp0()
> {
> data |= 1 << 4;
> _dirty = true;
> }
>
> /** This entry needs to be written back to memory */
> bool dirty() const
> {
> return _dirty;
> }
>
254a310
> void memAttrs(TlbEntry &te, uint8_t texcb, bool s);
257d312
< void memAttrs(TlbEntry &te, uint8_t texcb);