3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 41#define __ARCH_ARM_TABLE_WALKER_HH__ 42 43#include <list> 44 45#include "arch/arm/miscregs.hh" 46#include "arch/arm/tlb.hh" 47#include "dev/io_device.hh" 48#include "mem/mem_object.hh" 49#include "mem/request.hh" 50#include "params/ArmTableWalker.hh" 51#include "sim/eventq.hh" 52#include "sim/fault_fwd.hh" 53
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 41#define __ARCH_ARM_TABLE_WALKER_HH__ 42 43#include <list> 44 45#include "arch/arm/miscregs.hh" 46#include "arch/arm/tlb.hh" 47#include "dev/io_device.hh" 48#include "mem/mem_object.hh" 49#include "mem/request.hh" 50#include "params/ArmTableWalker.hh" 51#include "sim/eventq.hh" 52#include "sim/fault_fwd.hh" 53
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55class ThreadContext; 56 57namespace ArmISA { 58class Translation; 59class TLB; 60 61class TableWalker : public MemObject 62{ 63 public: 64 struct L1Descriptor { 65 /** Type of page table entry ARM DDI 0406B: B3-8*/ 66 enum EntryType { 67 Ignore, 68 PageTable, 69 Section, 70 Reserved 71 }; 72 73 /** The raw bits of the entry */ 74 uint32_t data; 75 76 /** This entry has been modified (access flag set) and needs to be 77 * written back to memory */ 78 bool _dirty; 79 80 EntryType type() const 81 { 82 return (EntryType)(data & 0x3); 83 } 84 85 /** Is the page a Supersection (16MB)?*/ 86 bool supersection() const 87 { 88 return bits(data, 18); 89 } 90 91 /** Return the physcal address of the entry, bits in position*/ 92 Addr paddr() const 93 { 94 if (supersection()) 95 panic("Super sections not implemented\n"); 96 return mbits(data, 31, 20); 97 } 98 /** Return the physcal address of the entry, bits in position*/ 99 Addr paddr(Addr va) const 100 { 101 if (supersection()) 102 panic("Super sections not implemented\n"); 103 return mbits(data, 31, 20) | mbits(va, 19, 0); 104 } 105 106 107 /** Return the physical frame, bits shifted right */ 108 Addr pfn() const 109 { 110 if (supersection()) 111 panic("Super sections not implemented\n"); 112 return bits(data, 31, 20); 113 } 114 115 /** Is the translation global (no asid used)? */ 116 bool global() const 117 { 118 return bits(data, 17); 119 } 120 121 /** Is the translation not allow execution? */ 122 bool xn() const 123 { 124 return bits(data, 4); 125 } 126 127 /** Three bit access protection flags */ 128 uint8_t ap() const 129 { 130 return (bits(data, 15) << 2) | bits(data, 11, 10); 131 } 132 133 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 134 uint8_t domain() const 135 { 136 return bits(data, 8, 5); 137 } 138 139 /** Address of L2 descriptor if it exists */ 140 Addr l2Addr() const 141 { 142 return mbits(data, 31, 10); 143 } 144 145 /** Memory region attributes: ARM DDI 0406B: B3-32. 146 * These bits are largly ignored by M5 and only used to 147 * provide the illusion that the memory system cares about 148 * anything but cachable vs. uncachable. 149 */ 150 uint8_t texcb() const 151 { 152 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 153 } 154 155 /** If the section is shareable. See texcb() comment. */ 156 bool shareable() const 157 { 158 return bits(data, 16); 159 } 160 161 /** Set access flag that this entry has been touched. Mark 162 * the entry as requiring a writeback, in the future. 163 */ 164 void setAp0() 165 { 166 data |= 1 << 10; 167 _dirty = true; 168 } 169 170 /** This entry needs to be written back to memory */ 171 bool dirty() const 172 { 173 return _dirty; 174 } 175 }; 176 177 /** Level 2 page table descriptor */ 178 struct L2Descriptor { 179 180 /** The raw bits of the entry. */ 181 uint32_t data; 182 183 /** This entry has been modified (access flag set) and needs to be 184 * written back to memory */ 185 bool _dirty; 186 187 /** Is the entry invalid */ 188 bool invalid() const 189 { 190 return bits(data, 1, 0) == 0; 191 } 192 193 /** What is the size of the mapping? */ 194 bool large() const 195 { 196 return bits(data, 1) == 0; 197 } 198 199 /** Is execution allowed on this mapping? */ 200 bool xn() const 201 { 202 return large() ? bits(data, 15) : bits(data, 0); 203 } 204 205 /** Is the translation global (no asid used)? */ 206 bool global() const 207 { 208 return !bits(data, 11); 209 } 210 211 /** Three bit access protection flags */ 212 uint8_t ap() const 213 { 214 return bits(data, 5, 4) | (bits(data, 9) << 2); 215 } 216 217 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 218 uint8_t texcb() const 219 { 220 return large() ? 221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 222 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 223 } 224 225 /** Return the physical frame, bits shifted right */ 226 Addr pfn() const 227 { 228 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 229 } 230 231 /** Return complete physical address given a VA */ 232 Addr paddr(Addr va) const 233 { 234 if (large()) 235 return mbits(data, 31, 16) | mbits(va, 15, 0); 236 else 237 return mbits(data, 31, 12) | mbits(va, 11, 0); 238 } 239 240 /** If the section is shareable. See texcb() comment. */ 241 bool shareable() const 242 { 243 return bits(data, 10); 244 } 245 246 /** Set access flag that this entry has been touched. Mark 247 * the entry as requiring a writeback, in the future. 248 */ 249 void setAp0() 250 { 251 data |= 1 << 4; 252 _dirty = true; 253 } 254 255 /** This entry needs to be written back to memory */ 256 bool dirty() const 257 { 258 return _dirty; 259 } 260 261 }; 262
| 54class ThreadContext; 55 56namespace ArmISA { 57class Translation; 58class TLB; 59 60class TableWalker : public MemObject 61{ 62 public: 63 struct L1Descriptor { 64 /** Type of page table entry ARM DDI 0406B: B3-8*/ 65 enum EntryType { 66 Ignore, 67 PageTable, 68 Section, 69 Reserved 70 }; 71 72 /** The raw bits of the entry */ 73 uint32_t data; 74 75 /** This entry has been modified (access flag set) and needs to be 76 * written back to memory */ 77 bool _dirty; 78 79 EntryType type() const 80 { 81 return (EntryType)(data & 0x3); 82 } 83 84 /** Is the page a Supersection (16MB)?*/ 85 bool supersection() const 86 { 87 return bits(data, 18); 88 } 89 90 /** Return the physcal address of the entry, bits in position*/ 91 Addr paddr() const 92 { 93 if (supersection()) 94 panic("Super sections not implemented\n"); 95 return mbits(data, 31, 20); 96 } 97 /** Return the physcal address of the entry, bits in position*/ 98 Addr paddr(Addr va) const 99 { 100 if (supersection()) 101 panic("Super sections not implemented\n"); 102 return mbits(data, 31, 20) | mbits(va, 19, 0); 103 } 104 105 106 /** Return the physical frame, bits shifted right */ 107 Addr pfn() const 108 { 109 if (supersection()) 110 panic("Super sections not implemented\n"); 111 return bits(data, 31, 20); 112 } 113 114 /** Is the translation global (no asid used)? */ 115 bool global() const 116 { 117 return bits(data, 17); 118 } 119 120 /** Is the translation not allow execution? */ 121 bool xn() const 122 { 123 return bits(data, 4); 124 } 125 126 /** Three bit access protection flags */ 127 uint8_t ap() const 128 { 129 return (bits(data, 15) << 2) | bits(data, 11, 10); 130 } 131 132 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 133 uint8_t domain() const 134 { 135 return bits(data, 8, 5); 136 } 137 138 /** Address of L2 descriptor if it exists */ 139 Addr l2Addr() const 140 { 141 return mbits(data, 31, 10); 142 } 143 144 /** Memory region attributes: ARM DDI 0406B: B3-32. 145 * These bits are largly ignored by M5 and only used to 146 * provide the illusion that the memory system cares about 147 * anything but cachable vs. uncachable. 148 */ 149 uint8_t texcb() const 150 { 151 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 152 } 153 154 /** If the section is shareable. See texcb() comment. */ 155 bool shareable() const 156 { 157 return bits(data, 16); 158 } 159 160 /** Set access flag that this entry has been touched. Mark 161 * the entry as requiring a writeback, in the future. 162 */ 163 void setAp0() 164 { 165 data |= 1 << 10; 166 _dirty = true; 167 } 168 169 /** This entry needs to be written back to memory */ 170 bool dirty() const 171 { 172 return _dirty; 173 } 174 }; 175 176 /** Level 2 page table descriptor */ 177 struct L2Descriptor { 178 179 /** The raw bits of the entry. */ 180 uint32_t data; 181 182 /** This entry has been modified (access flag set) and needs to be 183 * written back to memory */ 184 bool _dirty; 185 186 /** Is the entry invalid */ 187 bool invalid() const 188 { 189 return bits(data, 1, 0) == 0; 190 } 191 192 /** What is the size of the mapping? */ 193 bool large() const 194 { 195 return bits(data, 1) == 0; 196 } 197 198 /** Is execution allowed on this mapping? */ 199 bool xn() const 200 { 201 return large() ? bits(data, 15) : bits(data, 0); 202 } 203 204 /** Is the translation global (no asid used)? */ 205 bool global() const 206 { 207 return !bits(data, 11); 208 } 209 210 /** Three bit access protection flags */ 211 uint8_t ap() const 212 { 213 return bits(data, 5, 4) | (bits(data, 9) << 2); 214 } 215 216 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 217 uint8_t texcb() const 218 { 219 return large() ? 220 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 222 } 223 224 /** Return the physical frame, bits shifted right */ 225 Addr pfn() const 226 { 227 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 228 } 229 230 /** Return complete physical address given a VA */ 231 Addr paddr(Addr va) const 232 { 233 if (large()) 234 return mbits(data, 31, 16) | mbits(va, 15, 0); 235 else 236 return mbits(data, 31, 12) | mbits(va, 11, 0); 237 } 238 239 /** If the section is shareable. See texcb() comment. */ 240 bool shareable() const 241 { 242 return bits(data, 10); 243 } 244 245 /** Set access flag that this entry has been touched. Mark 246 * the entry as requiring a writeback, in the future. 247 */ 248 void setAp0() 249 { 250 data |= 1 << 4; 251 _dirty = true; 252 } 253 254 /** This entry needs to be written back to memory */ 255 bool dirty() const 256 { 257 return _dirty; 258 } 259 260 }; 261
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333 334 /** TLB that is initiating these table walks */ 335 TLB *tlb; 336 337 /** Cached copy of the sctlr as it existed when translation began */ 338 SCTLR sctlr; 339 340 WalkerState *currState; 341 342 /** If a timing translation is currently in progress */ 343 bool pending; 344 345 /** Request id for requests generated by this walker */ 346 MasterID masterId; 347 348 public: 349 typedef ArmTableWalkerParams Params; 350 TableWalker(const Params *p); 351 virtual ~TableWalker(); 352 353 const Params * 354 params() const 355 { 356 return dynamic_cast<const Params *>(_params); 357 } 358 359 virtual unsigned int drain(Event *de); 360 virtual void resume(); 361 virtual MasterPort& getMasterPort(const std::string &if_name, 362 int idx = -1); 363 364 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 365 TLB::Translation *_trans, bool timing, bool functional = false); 366 367 void setTlb(TLB *_tlb) { tlb = _tlb; } 368 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 369 uint8_t texcb, bool s); 370 371 private: 372 373 void doL1Descriptor(); 374 void doL1DescriptorWrapper(); 375 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 376 377 void doL2Descriptor(); 378 void doL2DescriptorWrapper(); 379 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 380 381 Fault processWalk(); 382 void processWalkWrapper(); 383 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 384 385 void nextWalk(ThreadContext *tc); 386}; 387 388 389} // namespace ArmISA 390 391#endif //__ARCH_ARM_TABLE_WALKER_HH__ 392
| 366 367 /** TLB that is initiating these table walks */ 368 TLB *tlb; 369 370 /** Cached copy of the sctlr as it existed when translation began */ 371 SCTLR sctlr; 372 373 WalkerState *currState; 374 375 /** If a timing translation is currently in progress */ 376 bool pending; 377 378 /** Request id for requests generated by this walker */ 379 MasterID masterId; 380 381 public: 382 typedef ArmTableWalkerParams Params; 383 TableWalker(const Params *p); 384 virtual ~TableWalker(); 385 386 const Params * 387 params() const 388 { 389 return dynamic_cast<const Params *>(_params); 390 } 391 392 virtual unsigned int drain(Event *de); 393 virtual void resume(); 394 virtual MasterPort& getMasterPort(const std::string &if_name, 395 int idx = -1); 396 397 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 398 TLB::Translation *_trans, bool timing, bool functional = false); 399 400 void setTlb(TLB *_tlb) { tlb = _tlb; } 401 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 402 uint8_t texcb, bool s); 403 404 private: 405 406 void doL1Descriptor(); 407 void doL1DescriptorWrapper(); 408 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 409 410 void doL2Descriptor(); 411 void doL2DescriptorWrapper(); 412 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 413 414 Fault processWalk(); 415 void processWalkWrapper(); 416 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 417 418 void nextWalk(ThreadContext *tc); 419}; 420 421 422} // namespace ArmISA 423 424#endif //__ARCH_ARM_TABLE_WALKER_HH__ 425
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