1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include "arch/arm/miscregs.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/mem_object.hh"
46#include "mem/request.hh"
47#include "mem/request.hh"
48#include "params/ArmTableWalker.hh"
49#include "sim/faults.hh"
50#include "sim/eventq.hh"
51
52class DmaPort;
53class ThreadContext;
54
55namespace ArmISA {
56class Translation;
57class TLB;
58
59class TableWalker : public MemObject
60{
61 protected:
62 struct L1Descriptor {
63 /** Type of page table entry ARM DDI 0406B: B3-8*/
64 enum EntryType {
65 Ignore,
66 PageTable,
67 Section,
68 Reserved
69 };
70
71 /** The raw bits of the entry */
72 uint32_t data;
73
74 /** This entry has been modified (access flag set) and needs to be
75 * written back to memory */
76 bool _dirty;
77
78 EntryType type() const
79 {
80 return (EntryType)(data & 0x3);
81 }
82
83 /** Is the page a Supersection (16MB)?*/
84 bool supersection() const
85 {
86 return bits(data, 18);
87 }
88
89 /** Return the physcal address of the entry, bits in position*/
90 Addr paddr() const
91 {
92 if (supersection())
93 panic("Super sections not implemented\n");
94 return mbits(data, 31,20);
95 }
96
97 /** Return the physical frame, bits shifted right */
98 Addr pfn() const
99 {
100 if (supersection())
101 panic("Super sections not implemented\n");
102 return bits(data, 31,20);
103 }
104
105 /** Is the translation global (no asid used)? */
106 bool global() const
107 {
108 return bits(data, 4);
109 }
110
111 /** Is the translation not allow execution? */
112 bool xn() const
113 {
114 return bits(data, 17);
115 }
116
117 /** Three bit access protection flags */
118 uint8_t ap() const
119 {
120 return (bits(data, 15) << 2) | bits(data,11,10);
121 }
122
123 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
124 uint8_t domain() const
125 {
126 return bits(data,8,5);
127 }
128
129 /** Address of L2 descriptor if it exists */
130 Addr l2Addr() const
131 {
132 return mbits(data, 31,10);
133 }
134
135 /** Memory region attributes: ARM DDI 0406B: B3-32.
136 * These bits are largly ignored by M5 and only used to
137 * provide the illusion that the memory system cares about
138 * anything but cachable vs. uncachable.
139 */
140 uint8_t texcb() const
141 {
142 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
143 }
144
145 /** If the section is shareable. See texcb() comment. */
146 bool shareable() const
147 {
148 return bits(data, 16);
149 }
150
151 /** Set access flag that this entry has been touched. Mark
152 * the entry as requiring a writeback, in the future.
153 */
154 void setAp0()
155 {
156 data |= 1 << 10;
157 _dirty = true;
158 }
159
160 /** This entry needs to be written back to memory */
161 bool dirty() const
162 {
163 return _dirty;
164 }
165 };
166
167 /** Level 2 page table descriptor */
168 struct L2Descriptor {
169
170 /** The raw bits of the entry. */
171 uint32_t data;
172
173 /** This entry has been modified (access flag set) and needs to be
174 * written back to memory */
175 bool _dirty;
176
177 /** Is the entry invalid */
178 bool invalid() const
179 {
180 return bits(data, 1,0) == 0;;
181 }
182
183 /** What is the size of the mapping? */
184 bool large() const
185 {
186 return bits(data, 1) == 0;
187 }
188
189 /** Is execution allowed on this mapping? */
190 bool xn() const
191 {
192 return large() ? bits(data, 15) : bits(data, 0);
193 }
194
195 /** Is the translation global (no asid used)? */
196 bool global() const
197 {
198 return !bits(data, 11);
199 }
200
201 /** Three bit access protection flags */
202 uint8_t ap() const
203 {
204 return bits(data, 5, 4) | (bits(data, 9) << 2);
205 }
206
207 /** Memory region attributes: ARM DDI 0406B: B3-32 */
208 uint8_t texcb() const
209 {
210 return large() ?
211 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
212 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
213 }
214
215 /** Return the physical frame, bits shifted right */
216 Addr pfn() const
217 {
218 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
219 }
220
221 /** If the section is shareable. See texcb() comment. */
222 bool shareable() const
223 {
224 return bits(data, 10);
225 }
226
227 /** Set access flag that this entry has been touched. Mark
228 * the entry as requiring a writeback, in the future.
229 */
230 void setAp0()
231 {
232 data |= 1 << 4;
233 _dirty = true;
234 }
235
236 /** This entry needs to be written back to memory */
237 bool dirty() const
238 {
239 return _dirty;
240 }
241
242 };
243
244 /** Port to issue translation requests from */
245 DmaPort *port;
246
247 /** TLB that is initiating these table walks */
248 TLB *tlb;
249
250 /** Thread context that we're doing the walk for */
251 ThreadContext *tc;
252
253 /** Request that is currently being serviced */
254 RequestPtr req;
255
256 /** Context ID that we're servicing the request under */
257 uint8_t contextId;
258
259 /** Translation state for delayed requests */
260 TLB::Translation *transState;
261
262 /** The fault that we are going to return */
263 Fault fault;
264
265 /** The virtual address that is being translated */
266 Addr vaddr;
267
268 /** Cached copy of the sctlr as it existed when translation began */
269 SCTLR sctlr;
270
271 /** Cached copy of the cpsr as it existed when the translation began */
272 CPSR cpsr;
273
274 /** Width of the base address held in TTRB0 */
275 uint32_t N;
276
277 /** If the access is a write */
278 bool isWrite;
279
280 /** If the access is not from user mode */
281 bool isPriv;
282
283 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
284 bool isFetch;
285
286 /** If the mode is timing or atomic */
287 bool timing;
288
289 L1Descriptor l1Desc;
290 L2Descriptor l2Desc;
291
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __ARCH_ARM_TABLE_WALKER_HH__
41#define __ARCH_ARM_TABLE_WALKER_HH__
42
43#include "arch/arm/miscregs.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/mem_object.hh"
46#include "mem/request.hh"
47#include "mem/request.hh"
48#include "params/ArmTableWalker.hh"
49#include "sim/faults.hh"
50#include "sim/eventq.hh"
51
52class DmaPort;
53class ThreadContext;
54
55namespace ArmISA {
56class Translation;
57class TLB;
58
59class TableWalker : public MemObject
60{
61 protected:
62 struct L1Descriptor {
63 /** Type of page table entry ARM DDI 0406B: B3-8*/
64 enum EntryType {
65 Ignore,
66 PageTable,
67 Section,
68 Reserved
69 };
70
71 /** The raw bits of the entry */
72 uint32_t data;
73
74 /** This entry has been modified (access flag set) and needs to be
75 * written back to memory */
76 bool _dirty;
77
78 EntryType type() const
79 {
80 return (EntryType)(data & 0x3);
81 }
82
83 /** Is the page a Supersection (16MB)?*/
84 bool supersection() const
85 {
86 return bits(data, 18);
87 }
88
89 /** Return the physcal address of the entry, bits in position*/
90 Addr paddr() const
91 {
92 if (supersection())
93 panic("Super sections not implemented\n");
94 return mbits(data, 31,20);
95 }
96
97 /** Return the physical frame, bits shifted right */
98 Addr pfn() const
99 {
100 if (supersection())
101 panic("Super sections not implemented\n");
102 return bits(data, 31,20);
103 }
104
105 /** Is the translation global (no asid used)? */
106 bool global() const
107 {
108 return bits(data, 4);
109 }
110
111 /** Is the translation not allow execution? */
112 bool xn() const
113 {
114 return bits(data, 17);
115 }
116
117 /** Three bit access protection flags */
118 uint8_t ap() const
119 {
120 return (bits(data, 15) << 2) | bits(data,11,10);
121 }
122
123 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
124 uint8_t domain() const
125 {
126 return bits(data,8,5);
127 }
128
129 /** Address of L2 descriptor if it exists */
130 Addr l2Addr() const
131 {
132 return mbits(data, 31,10);
133 }
134
135 /** Memory region attributes: ARM DDI 0406B: B3-32.
136 * These bits are largly ignored by M5 and only used to
137 * provide the illusion that the memory system cares about
138 * anything but cachable vs. uncachable.
139 */
140 uint8_t texcb() const
141 {
142 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
143 }
144
145 /** If the section is shareable. See texcb() comment. */
146 bool shareable() const
147 {
148 return bits(data, 16);
149 }
150
151 /** Set access flag that this entry has been touched. Mark
152 * the entry as requiring a writeback, in the future.
153 */
154 void setAp0()
155 {
156 data |= 1 << 10;
157 _dirty = true;
158 }
159
160 /** This entry needs to be written back to memory */
161 bool dirty() const
162 {
163 return _dirty;
164 }
165 };
166
167 /** Level 2 page table descriptor */
168 struct L2Descriptor {
169
170 /** The raw bits of the entry. */
171 uint32_t data;
172
173 /** This entry has been modified (access flag set) and needs to be
174 * written back to memory */
175 bool _dirty;
176
177 /** Is the entry invalid */
178 bool invalid() const
179 {
180 return bits(data, 1,0) == 0;;
181 }
182
183 /** What is the size of the mapping? */
184 bool large() const
185 {
186 return bits(data, 1) == 0;
187 }
188
189 /** Is execution allowed on this mapping? */
190 bool xn() const
191 {
192 return large() ? bits(data, 15) : bits(data, 0);
193 }
194
195 /** Is the translation global (no asid used)? */
196 bool global() const
197 {
198 return !bits(data, 11);
199 }
200
201 /** Three bit access protection flags */
202 uint8_t ap() const
203 {
204 return bits(data, 5, 4) | (bits(data, 9) << 2);
205 }
206
207 /** Memory region attributes: ARM DDI 0406B: B3-32 */
208 uint8_t texcb() const
209 {
210 return large() ?
211 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
212 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
213 }
214
215 /** Return the physical frame, bits shifted right */
216 Addr pfn() const
217 {
218 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
219 }
220
221 /** If the section is shareable. See texcb() comment. */
222 bool shareable() const
223 {
224 return bits(data, 10);
225 }
226
227 /** Set access flag that this entry has been touched. Mark
228 * the entry as requiring a writeback, in the future.
229 */
230 void setAp0()
231 {
232 data |= 1 << 4;
233 _dirty = true;
234 }
235
236 /** This entry needs to be written back to memory */
237 bool dirty() const
238 {
239 return _dirty;
240 }
241
242 };
243
244 /** Port to issue translation requests from */
245 DmaPort *port;
246
247 /** TLB that is initiating these table walks */
248 TLB *tlb;
249
250 /** Thread context that we're doing the walk for */
251 ThreadContext *tc;
252
253 /** Request that is currently being serviced */
254 RequestPtr req;
255
256 /** Context ID that we're servicing the request under */
257 uint8_t contextId;
258
259 /** Translation state for delayed requests */
260 TLB::Translation *transState;
261
262 /** The fault that we are going to return */
263 Fault fault;
264
265 /** The virtual address that is being translated */
266 Addr vaddr;
267
268 /** Cached copy of the sctlr as it existed when translation began */
269 SCTLR sctlr;
270
271 /** Cached copy of the cpsr as it existed when the translation began */
272 CPSR cpsr;
273
274 /** Width of the base address held in TTRB0 */
275 uint32_t N;
276
277 /** If the access is a write */
278 bool isWrite;
279
280 /** If the access is not from user mode */
281 bool isPriv;
282
283 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
284 bool isFetch;
285
286 /** If the mode is timing or atomic */
287 bool timing;
288
289 L1Descriptor l1Desc;
290 L2Descriptor l2Desc;
291
|