1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 41#define __ARCH_ARM_TABLE_WALKER_HH__ 42 43#include "arch/arm/miscregs.hh" 44#include "arch/arm/tlb.hh" 45#include "mem/mem_object.hh" 46#include "mem/request.hh" 47#include "mem/request.hh" 48#include "params/ArmTableWalker.hh" 49#include "sim/faults.hh" 50#include "sim/eventq.hh" 51 52class DmaPort; 53class ThreadContext; 54 55namespace ArmISA { 56class Translation; 57class TLB; 58 59class TableWalker : public MemObject 60{ 61 protected: 62 struct L1Descriptor { 63 /** Type of page table entry ARM DDI 0406B: B3-8*/ 64 enum EntryType { 65 Ignore, 66 PageTable, 67 Section, 68 Reserved 69 }; 70
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 41#define __ARCH_ARM_TABLE_WALKER_HH__ 42 43#include "arch/arm/miscregs.hh" 44#include "arch/arm/tlb.hh" 45#include "mem/mem_object.hh" 46#include "mem/request.hh" 47#include "mem/request.hh" 48#include "params/ArmTableWalker.hh" 49#include "sim/faults.hh" 50#include "sim/eventq.hh" 51 52class DmaPort; 53class ThreadContext; 54 55namespace ArmISA { 56class Translation; 57class TLB; 58 59class TableWalker : public MemObject 60{ 61 protected: 62 struct L1Descriptor { 63 /** Type of page table entry ARM DDI 0406B: B3-8*/ 64 enum EntryType { 65 Ignore, 66 PageTable, 67 Section, 68 Reserved 69 }; 70
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| 71 /** The raw bits of the entry */
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71 uint32_t data; 72
| 72 uint32_t data; 73
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| 74 /** This entry has been modified (access flag set) and needs to be 75 * written back to memory */ 76 bool _dirty; 77
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73 EntryType type() const 74 { 75 return (EntryType)(data & 0x3); 76 } 77 78 /** Is the page a Supersection (16MB)?*/ 79 bool supersection() const 80 { 81 return bits(data, 18); 82 } 83 84 /** Return the physcal address of the entry, bits in position*/ 85 Addr paddr() const 86 { 87 if (supersection()) 88 panic("Super sections not implemented\n"); 89 return mbits(data, 31,20); 90 } 91 92 /** Return the physical frame, bits shifted right */ 93 Addr pfn() const 94 { 95 if (supersection()) 96 panic("Super sections not implemented\n"); 97 return bits(data, 31,20); 98 } 99 100 /** Is the translation global (no asid used)? */ 101 bool global() const 102 { 103 return bits(data, 4); 104 } 105 106 /** Is the translation not allow execution? */ 107 bool xn() const 108 { 109 return bits(data, 17); 110 } 111 112 /** Three bit access protection flags */ 113 uint8_t ap() const 114 { 115 return (bits(data, 15) << 2) | bits(data,11,10); 116 } 117 118 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 119 uint8_t domain() const 120 { 121 return bits(data,8,5); 122 } 123 124 /** Address of L2 descriptor if it exists */ 125 Addr l2Addr() const 126 { 127 return mbits(data, 31,10); 128 } 129
| 78 EntryType type() const 79 { 80 return (EntryType)(data & 0x3); 81 } 82 83 /** Is the page a Supersection (16MB)?*/ 84 bool supersection() const 85 { 86 return bits(data, 18); 87 } 88 89 /** Return the physcal address of the entry, bits in position*/ 90 Addr paddr() const 91 { 92 if (supersection()) 93 panic("Super sections not implemented\n"); 94 return mbits(data, 31,20); 95 } 96 97 /** Return the physical frame, bits shifted right */ 98 Addr pfn() const 99 { 100 if (supersection()) 101 panic("Super sections not implemented\n"); 102 return bits(data, 31,20); 103 } 104 105 /** Is the translation global (no asid used)? */ 106 bool global() const 107 { 108 return bits(data, 4); 109 } 110 111 /** Is the translation not allow execution? */ 112 bool xn() const 113 { 114 return bits(data, 17); 115 } 116 117 /** Three bit access protection flags */ 118 uint8_t ap() const 119 { 120 return (bits(data, 15) << 2) | bits(data,11,10); 121 } 122 123 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 124 uint8_t domain() const 125 { 126 return bits(data,8,5); 127 } 128 129 /** Address of L2 descriptor if it exists */ 130 Addr l2Addr() const 131 { 132 return mbits(data, 31,10); 133 } 134
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130 /** Memory region attributes: ARM DDI 0406B: B3-32 */
| 135 /** Memory region attributes: ARM DDI 0406B: B3-32. 136 * These bits are largly ignored by M5 and only used to 137 * provide the illusion that the memory system cares about 138 * anything but cachable vs. uncachable. 139 */
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131 uint8_t texcb() const 132 { 133 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; 134 } 135
| 140 uint8_t texcb() const 141 { 142 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; 143 } 144
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| 145 /** If the section is shareable. See texcb() comment. */ 146 bool shareable() const 147 { 148 return bits(data, 16); 149 } 150 151 /** Set access flag that this entry has been touched. Mark 152 * the entry as requiring a writeback, in the future. 153 */ 154 void setAp0() 155 { 156 data |= 1 << 10; 157 _dirty = true; 158 } 159 160 /** This entry needs to be written back to memory */ 161 bool dirty() const 162 { 163 return _dirty; 164 }
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136 }; 137 138 /** Level 2 page table descriptor */ 139 struct L2Descriptor { 140
| 165 }; 166 167 /** Level 2 page table descriptor */ 168 struct L2Descriptor { 169
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| 170 /** The raw bits of the entry. */
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141 uint32_t data; 142
| 171 uint32_t data; 172
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| 173 /** This entry has been modified (access flag set) and needs to be 174 * written back to memory */ 175 bool _dirty; 176
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143 /** Is the entry invalid */ 144 bool invalid() const 145 { 146 return bits(data, 1,0) == 0;; 147 } 148 149 /** What is the size of the mapping? */ 150 bool large() const 151 { 152 return bits(data, 1) == 0; 153 } 154 155 /** Is execution allowed on this mapping? */ 156 bool xn() const 157 { 158 return large() ? bits(data, 15) : bits(data, 0); 159 } 160 161 /** Is the translation global (no asid used)? */ 162 bool global() const 163 { 164 return !bits(data, 11); 165 } 166 167 /** Three bit access protection flags */ 168 uint8_t ap() const 169 { 170 return bits(data, 5, 4) | (bits(data, 9) << 2); 171 } 172 173 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 174 uint8_t texcb() const 175 { 176 return large() ? 177 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) : 178 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2)); 179 } 180 181 /** Return the physical frame, bits shifted right */ 182 Addr pfn() const 183 { 184 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 185 } 186
| 177 /** Is the entry invalid */ 178 bool invalid() const 179 { 180 return bits(data, 1,0) == 0;; 181 } 182 183 /** What is the size of the mapping? */ 184 bool large() const 185 { 186 return bits(data, 1) == 0; 187 } 188 189 /** Is execution allowed on this mapping? */ 190 bool xn() const 191 { 192 return large() ? bits(data, 15) : bits(data, 0); 193 } 194 195 /** Is the translation global (no asid used)? */ 196 bool global() const 197 { 198 return !bits(data, 11); 199 } 200 201 /** Three bit access protection flags */ 202 uint8_t ap() const 203 { 204 return bits(data, 5, 4) | (bits(data, 9) << 2); 205 } 206 207 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 208 uint8_t texcb() const 209 { 210 return large() ? 211 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) : 212 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2)); 213 } 214 215 /** Return the physical frame, bits shifted right */ 216 Addr pfn() const 217 { 218 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 219 } 220
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| 221 /** If the section is shareable. See texcb() comment. */ 222 bool shareable() const 223 { 224 return bits(data, 10); 225 } 226 227 /** Set access flag that this entry has been touched. Mark 228 * the entry as requiring a writeback, in the future. 229 */ 230 void setAp0() 231 { 232 data |= 1 << 4; 233 _dirty = true; 234 } 235 236 /** This entry needs to be written back to memory */ 237 bool dirty() const 238 { 239 return _dirty; 240 } 241
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187 }; 188 189 /** Port to issue translation requests from */ 190 DmaPort *port; 191 192 /** TLB that is initiating these table walks */ 193 TLB *tlb; 194 195 /** Thread context that we're doing the walk for */ 196 ThreadContext *tc; 197 198 /** Request that is currently being serviced */ 199 RequestPtr req; 200 201 /** Context ID that we're servicing the request under */ 202 uint8_t contextId; 203 204 /** Translation state for delayed requests */ 205 TLB::Translation *transState; 206 207 /** The fault that we are going to return */ 208 Fault fault; 209 210 /** The virtual address that is being translated */ 211 Addr vaddr; 212 213 /** Cached copy of the sctlr as it existed when translation began */ 214 SCTLR sctlr; 215 216 /** Cached copy of the cpsr as it existed when the translation began */ 217 CPSR cpsr; 218 219 /** Width of the base address held in TTRB0 */ 220 uint32_t N; 221 222 /** If the access is a write */ 223 bool isWrite; 224 225 /** If the access is not from user mode */ 226 bool isPriv; 227 228 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 229 bool isFetch; 230 231 /** If the mode is timing or atomic */ 232 bool timing; 233 234 L1Descriptor l1Desc; 235 L2Descriptor l2Desc; 236 237 public: 238 typedef ArmTableWalkerParams Params; 239 TableWalker(const Params *p); 240 virtual ~TableWalker(); 241 242 const Params * 243 params() const 244 { 245 return dynamic_cast<const Params *>(_params); 246 } 247 248 virtual unsigned int drain(Event *de) { panic("write me\n"); } 249 virtual Port *getPort(const std::string &if_name, int idx = -1); 250 251 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 252 TLB::Translation *_trans, bool timing); 253 254 void setTlb(TLB *_tlb) { tlb = _tlb; }
| 242 }; 243 244 /** Port to issue translation requests from */ 245 DmaPort *port; 246 247 /** TLB that is initiating these table walks */ 248 TLB *tlb; 249 250 /** Thread context that we're doing the walk for */ 251 ThreadContext *tc; 252 253 /** Request that is currently being serviced */ 254 RequestPtr req; 255 256 /** Context ID that we're servicing the request under */ 257 uint8_t contextId; 258 259 /** Translation state for delayed requests */ 260 TLB::Translation *transState; 261 262 /** The fault that we are going to return */ 263 Fault fault; 264 265 /** The virtual address that is being translated */ 266 Addr vaddr; 267 268 /** Cached copy of the sctlr as it existed when translation began */ 269 SCTLR sctlr; 270 271 /** Cached copy of the cpsr as it existed when the translation began */ 272 CPSR cpsr; 273 274 /** Width of the base address held in TTRB0 */ 275 uint32_t N; 276 277 /** If the access is a write */ 278 bool isWrite; 279 280 /** If the access is not from user mode */ 281 bool isPriv; 282 283 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 284 bool isFetch; 285 286 /** If the mode is timing or atomic */ 287 bool timing; 288 289 L1Descriptor l1Desc; 290 L2Descriptor l2Desc; 291 292 public: 293 typedef ArmTableWalkerParams Params; 294 TableWalker(const Params *p); 295 virtual ~TableWalker(); 296 297 const Params * 298 params() const 299 { 300 return dynamic_cast<const Params *>(_params); 301 } 302 303 virtual unsigned int drain(Event *de) { panic("write me\n"); } 304 virtual Port *getPort(const std::string &if_name, int idx = -1); 305 306 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 307 TLB::Translation *_trans, bool timing); 308 309 void setTlb(TLB *_tlb) { tlb = _tlb; }
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| 310 void memAttrs(TlbEntry &te, uint8_t texcb, bool s);
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255 256 private:
| 311 312 private:
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257 void memAttrs(TlbEntry &te, uint8_t texcb);
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258 259 void doL1Descriptor(); 260 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent; 261 262 void doL2Descriptor(); 263 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent; 264 265 266}; 267 268 269} // namespace ArmISA 270 271#endif //__ARCH_ARM_TABLE_WALKER_HH__ 272
| 313 314 void doL1Descriptor(); 315 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent; 316 317 void doL2Descriptor(); 318 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent; 319 320 321}; 322 323 324} // namespace ArmISA 325 326#endif //__ARCH_ARM_TABLE_WALKER_HH__ 327
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