table_walker.hh (7438:8e4b37136330) | table_walker.hh (7439:b4c6b2532bbf) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43#include "arch/arm/miscregs.hh" 44#include "arch/arm/tlb.hh" 45#include "mem/mem_object.hh" 46#include "mem/request.hh" 47#include "mem/request.hh" 48#include "params/ArmTableWalker.hh" 49#include "sim/faults.hh" 50#include "sim/eventq.hh" | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43#include "arch/arm/miscregs.hh" 44#include "arch/arm/tlb.hh" 45#include "mem/mem_object.hh" 46#include "mem/request.hh" 47#include "mem/request.hh" 48#include "params/ArmTableWalker.hh" 49#include "sim/faults.hh" 50#include "sim/eventq.hh" |
51#include "base/fifo_buffer.hh" |
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51 52class DmaPort; 53class ThreadContext; 54 55namespace ArmISA { 56class Translation; 57class TLB; 58 --- 177 unchanged lines hidden (view full) --- 236 /** This entry needs to be written back to memory */ 237 bool dirty() const 238 { 239 return _dirty; 240 } 241 242 }; 243 | 52 53class DmaPort; 54class ThreadContext; 55 56namespace ArmISA { 57class Translation; 58class TLB; 59 --- 177 unchanged lines hidden (view full) --- 237 /** This entry needs to be written back to memory */ 238 bool dirty() const 239 { 240 return _dirty; 241 } 242 243 }; 244 |
244 /** Port to issue translation requests from */ 245 DmaPort *port; | 245 struct WalkerState //: public SimObject 246 { 247 /** Thread context that we're doing the walk for */ 248 ThreadContext *tc; |
246 | 249 |
247 /** TLB that is initiating these table walks */ 248 TLB *tlb; | 250 /** Request that is currently being serviced */ 251 RequestPtr req; |
249 | 252 |
250 /** Thread context that we're doing the walk for */ 251 ThreadContext *tc; | 253 /** Context ID that we're servicing the request under */ 254 uint8_t contextId; |
252 | 255 |
253 /** Request that is currently being serviced */ 254 RequestPtr req; | 256 /** Translation state for delayed requests */ 257 TLB::Translation *transState; |
255 | 258 |
256 /** Context ID that we're servicing the request under */ 257 uint8_t contextId; | 259 /** The fault that we are going to return */ 260 Fault fault; |
258 | 261 |
259 /** Translation state for delayed requests */ 260 TLB::Translation *transState; | 262 /** The virtual address that is being translated */ 263 Addr vaddr; |
261 | 264 |
262 /** The fault that we are going to return */ 263 Fault fault; | 265 /** Cached copy of the sctlr as it existed when translation began */ 266 SCTLR sctlr; |
264 | 267 |
265 /** The virtual address that is being translated */ 266 Addr vaddr; | 268 /** Cached copy of the cpsr as it existed when the translation began */ 269 CPSR cpsr; |
267 | 270 |
268 /** Cached copy of the sctlr as it existed when translation began */ 269 SCTLR sctlr; | 271 /** Width of the base address held in TTRB0 */ 272 uint32_t N; |
270 | 273 |
271 /** Cached copy of the cpsr as it existed when the translation began */ 272 CPSR cpsr; | 274 /** If the access is a write */ 275 bool isWrite; |
273 | 276 |
274 /** Width of the base address held in TTRB0 */ 275 uint32_t N; | 277 /** If the access is not from user mode */ 278 bool isPriv; |
276 | 279 |
277 /** If the access is a write */ 278 bool isWrite; | 280 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 281 bool isFetch; |
279 | 282 |
280 /** If the access is not from user mode */ 281 bool isPriv; | 283 /** If the mode is timing or atomic */ 284 bool timing; |
282 | 285 |
283 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 284 bool isFetch; | 286 /** Save mode for use in delayed response */ 287 BaseTLB::Mode mode; |
285 | 288 |
286 /** If the mode is timing or atomic */ 287 bool timing; | 289 L1Descriptor l1Desc; 290 L2Descriptor l2Desc; |
288 | 291 |
289 L1Descriptor l1Desc; 290 L2Descriptor l2Desc; | 292 /** Whether L1/L2 descriptor response is delayed in timing mode */ 293 bool delayed; |
291 | 294 |
292 /** Save mode for use in delayed response */ 293 BaseTLB::Mode mode; | 295 TableWalker *tableWalker; |
294 | 296 |
295 /** Whether L1/L2 descriptor response is delayed in timing mode */ 296 bool delayed; | 297 void doL1Descriptor(); 298 void doL2Descriptor(); |
297 | 299 |
300 std::string name() const {return tableWalker->name();} 301 }; 302 303 304 FifoBuffer<WalkerState> stateQueue; 305 306 /** Port to issue translation requests from */ 307 DmaPort *port; 308 309 /** TLB that is initiating these table walks */ 310 TLB *tlb; 311 312 /** Cached copy of the sctlr as it existed when translation began */ 313 SCTLR sctlr; 314 315 WalkerState *currState; 316 |
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298 public: 299 typedef ArmTableWalkerParams Params; 300 TableWalker(const Params *p); 301 virtual ~TableWalker(); 302 303 const Params * 304 params() const 305 { 306 return dynamic_cast<const Params *>(_params); 307 } 308 309 virtual unsigned int drain(Event *de) { panic("write me\n"); } 310 virtual Port *getPort(const std::string &if_name, int idx = -1); 311 312 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 313 TLB::Translation *_trans, bool timing); 314 315 void setTlb(TLB *_tlb) { tlb = _tlb; } | 317 public: 318 typedef ArmTableWalkerParams Params; 319 TableWalker(const Params *p); 320 virtual ~TableWalker(); 321 322 const Params * 323 params() const 324 { 325 return dynamic_cast<const Params *>(_params); 326 } 327 328 virtual unsigned int drain(Event *de) { panic("write me\n"); } 329 virtual Port *getPort(const std::string &if_name, int idx = -1); 330 331 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 332 TLB::Translation *_trans, bool timing); 333 334 void setTlb(TLB *_tlb) { tlb = _tlb; } |
316 void memAttrs(ThreadContext *tc, TlbEntry &te, uint8_t texcb, bool s); | 335 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 336 uint8_t texcb, bool s); |
317 318 private: 319 320 void doL1Descriptor(); 321 void doL1DescriptorWrapper(); 322 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 323 324 void doL2Descriptor(); 325 void doL2DescriptorWrapper(); 326 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 327 328 329}; 330 331 332} // namespace ArmISA 333 334#endif //__ARCH_ARM_TABLE_WALKER_HH__ 335 | 337 338 private: 339 340 void doL1Descriptor(); 341 void doL1DescriptorWrapper(); 342 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 343 344 void doL2Descriptor(); 345 void doL2DescriptorWrapper(); 346 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 347 348 349}; 350 351 352} // namespace ArmISA 353 354#endif //__ARCH_ARM_TABLE_WALKER_HH__ 355 |