1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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46#include "arch/arm/tlb.hh"
47#include "dev/io_device.hh"
48#include "mem/mem_object.hh"
49#include "mem/request.hh"
50#include "params/ArmTableWalker.hh"
51#include "sim/eventq.hh"
52#include "sim/fault_fwd.hh"
53
54class DmaPort;
55class ThreadContext;
56
57namespace ArmISA {
58class Translation;
59class TLB;
60
61class TableWalker : public MemObject
62{

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255 /** This entry needs to be written back to memory */
256 bool dirty() const
257 {
258 return _dirty;
259 }
260
261 };
262
263 struct WalkerState //: public SimObject
264 {
265 /** Thread context that we're doing the walk for */
266 ThreadContext *tc;
267
268 /** Request that is currently being serviced */
269 RequestPtr req;
270

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324 std::list<WalkerState *> stateQueueL2;
325
326 /** Queue of requests that have passed are waiting because the walker is
327 * currently busy. */
328 std::list<WalkerState *> pendingQueue;
329
330
331 /** Port to issue translation requests from */
332 DmaPort port;
333
334 /** TLB that is initiating these table walks */
335 TLB *tlb;
336
337 /** Cached copy of the sctlr as it existed when translation began */
338 SCTLR sctlr;
339
340 WalkerState *currState;

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