1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "arch/arm/miscregs.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/mem_object.hh"
46#include "mem/request.hh"
47#include "mem/request.hh"
48#include "params/ArmTableWalker.hh"
49#include "sim/faults.hh"
50#include "sim/eventq.hh"
51
52class DmaPort;
53class ThreadContext;
54
55namespace ArmISA {
56class Translation;
57class TLB;
58

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236 /** This entry needs to be written back to memory */
237 bool dirty() const
238 {
239 return _dirty;
240 }
241
242 };
243
244 /** Port to issue translation requests from */
245 DmaPort *port;
246
247 /** TLB that is initiating these table walks */
248 TLB *tlb;
249
250 /** Thread context that we're doing the walk for */
251 ThreadContext *tc;
252
253 /** Request that is currently being serviced */
254 RequestPtr req;
255
256 /** Context ID that we're servicing the request under */
257 uint8_t contextId;
258
259 /** Translation state for delayed requests */
260 TLB::Translation *transState;
261
262 /** The fault that we are going to return */
263 Fault fault;
264
265 /** The virtual address that is being translated */
266 Addr vaddr;
267
268 /** Cached copy of the sctlr as it existed when translation began */
269 SCTLR sctlr;
270
271 /** Cached copy of the cpsr as it existed when the translation began */
272 CPSR cpsr;
273
274 /** Width of the base address held in TTRB0 */
275 uint32_t N;
276
277 /** If the access is a write */
278 bool isWrite;
279
280 /** If the access is not from user mode */
281 bool isPriv;
282
283 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
284 bool isFetch;
285
286 /** If the mode is timing or atomic */
287 bool timing;
288
289 L1Descriptor l1Desc;
290 L2Descriptor l2Desc;
291
292 /** Save mode for use in delayed response */
293 BaseTLB::Mode mode;
294
295 /** Whether L1/L2 descriptor response is delayed in timing mode */
296 bool delayed;
297
298 public:
299 typedef ArmTableWalkerParams Params;
300 TableWalker(const Params *p);
301 virtual ~TableWalker();
302
303 const Params *
304 params() const
305 {
306 return dynamic_cast<const Params *>(_params);
307 }
308
309 virtual unsigned int drain(Event *de) { panic("write me\n"); }
310 virtual Port *getPort(const std::string &if_name, int idx = -1);
311
312 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
313 TLB::Translation *_trans, bool timing);
314
315 void setTlb(TLB *_tlb) { tlb = _tlb; }
316 void memAttrs(ThreadContext *tc, TlbEntry &te, uint8_t texcb, bool s);
317
318 private:
319
320 void doL1Descriptor();
321 void doL1DescriptorWrapper();
322 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
323
324 void doL2Descriptor();
325 void doL2DescriptorWrapper();
326 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
327
328
329};
330
331
332} // namespace ArmISA
333
334#endif //__ARCH_ARM_TABLE_WALKER_HH__
335