1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "arch/arm/miscregs.hh"
44#include "arch/arm/tlb.hh"
45#include "mem/mem_object.hh"
46#include "mem/request.hh"
47#include "mem/request.hh"
48#include "params/ArmTableWalker.hh"
49#include "sim/faults.hh"
50#include "sim/eventq.hh"
51#include "base/fifo_buffer.hh"
52
53class DmaPort;
54class ThreadContext;
55
56namespace ArmISA {
57class Translation;
58class TLB;
59

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237 /** This entry needs to be written back to memory */
238 bool dirty() const
239 {
240 return _dirty;
241 }
242
243 };
244
245 struct WalkerState //: public SimObject
246 {
247 /** Thread context that we're doing the walk for */
248 ThreadContext *tc;
249
250 /** Request that is currently being serviced */
251 RequestPtr req;
252
253 /** Context ID that we're servicing the request under */
254 uint8_t contextId;
255
256 /** Translation state for delayed requests */
257 TLB::Translation *transState;
258
259 /** The fault that we are going to return */
260 Fault fault;
261
262 /** The virtual address that is being translated */
263 Addr vaddr;
264
265 /** Cached copy of the sctlr as it existed when translation began */
266 SCTLR sctlr;
267
268 /** Cached copy of the cpsr as it existed when the translation began */
269 CPSR cpsr;
270
271 /** Width of the base address held in TTRB0 */
272 uint32_t N;
273
274 /** If the access is a write */
275 bool isWrite;
276
277 /** If the access is not from user mode */
278 bool isPriv;
279
280 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
281 bool isFetch;
282
283 /** If the mode is timing or atomic */
284 bool timing;
285
286 /** Save mode for use in delayed response */
287 BaseTLB::Mode mode;
288
289 L1Descriptor l1Desc;
290 L2Descriptor l2Desc;
291
292 /** Whether L1/L2 descriptor response is delayed in timing mode */
293 bool delayed;
294
295 TableWalker *tableWalker;
296
297 void doL1Descriptor();
298 void doL2Descriptor();
299
300 std::string name() const {return tableWalker->name();}
301 };
302
303
304 FifoBuffer<WalkerState> stateQueue;
305
306 /** Port to issue translation requests from */
307 DmaPort *port;
308
309 /** TLB that is initiating these table walks */
310 TLB *tlb;
311
312 /** Cached copy of the sctlr as it existed when translation began */
313 SCTLR sctlr;
314
315 WalkerState *currState;
316
317 public:
318 typedef ArmTableWalkerParams Params;
319 TableWalker(const Params *p);
320 virtual ~TableWalker();
321
322 const Params *
323 params() const
324 {
325 return dynamic_cast<const Params *>(_params);
326 }
327
328 virtual unsigned int drain(Event *de) { panic("write me\n"); }
329 virtual Port *getPort(const std::string &if_name, int idx = -1);
330
331 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
332 TLB::Translation *_trans, bool timing);
333
334 void setTlb(TLB *_tlb) { tlb = _tlb; }
335 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
336 uint8_t texcb, bool s);
337
338 private:
339
340 void doL1Descriptor();
341 void doL1DescriptorWrapper();
342 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
343
344 void doL2Descriptor();
345 void doL2DescriptorWrapper();
346 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
347
348
349};
350
351
352} // namespace ArmISA
353
354#endif //__ARCH_ARM_TABLE_WALKER_HH__
355