table_walker.cc (9535:508aebb47ca6) table_walker.cc (10024:fc10e1f9f124)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 294 unchanged lines hidden (view full) ---

303 } else if (!currState->functional) {
304 port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
305 NULL, (uint8_t*)&currState->l1Desc.data,
306 currState->tc->getCpuPtr()->clockPeriod(), flag);
307 doL1Descriptor();
308 f = currState->fault;
309 } else {
310 RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 294 unchanged lines hidden (view full) ---

303 } else if (!currState->functional) {
304 port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
305 NULL, (uint8_t*)&currState->l1Desc.data,
306 currState->tc->getCpuPtr()->clockPeriod(), flag);
307 doL1Descriptor();
308 f = currState->fault;
309 } else {
310 RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
311 req->taskId(ContextSwitchTaskId::DMA);
311 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
312 pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
313 port.sendFunctional(pkt);
314 doL1Descriptor();
315 delete req;
316 delete pkt;
317 f = currState->fault;
318 }

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648 } else if (!currState->functional) {
649 port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
650 NULL, (uint8_t*)&currState->l2Desc.data,
651 currState->tc->getCpuPtr()->clockPeriod());
652 doL2Descriptor();
653 } else {
654 RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
655 masterId);
312 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
313 pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
314 port.sendFunctional(pkt);
315 doL1Descriptor();
316 delete req;
317 delete pkt;
318 f = currState->fault;
319 }

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649 } else if (!currState->functional) {
650 port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
651 NULL, (uint8_t*)&currState->l2Desc.data,
652 currState->tc->getCpuPtr()->clockPeriod());
653 doL2Descriptor();
654 } else {
655 RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
656 masterId);
657 req->taskId(ContextSwitchTaskId::DMA);
656 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
657 pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
658 port.sendFunctional(pkt);
659 doL2Descriptor();
660 delete req;
661 delete pkt;
662 }
663 return;

--- 163 unchanged lines hidden --- 		658 PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
659 pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
660 port.sendFunctional(pkt);
661 doL2Descriptor();
662 delete req;
663 delete pkt;
664 }
665 return;

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