table_walker.cc (8832:247fee427324) table_walker.cc (8851:7e966326ef5b)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40#include "arch/arm/faults.hh"
41#include "arch/arm/table_walker.hh"
42#include "arch/arm/tlb.hh"
43#include "cpu/base.hh"
44#include "cpu/thread_context.hh"
45#include "debug/Checkpoint.hh"
46#include "debug/TLB.hh"
47#include "debug/TLBVerbose.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40#include "arch/arm/faults.hh"
41#include "arch/arm/table_walker.hh"
42#include "arch/arm/tlb.hh"
43#include "cpu/base.hh"
44#include "cpu/thread_context.hh"
45#include "debug/Checkpoint.hh"
46#include "debug/TLB.hh"
47#include "debug/TLBVerbose.hh"
48#include "dev/io_device.hh"
49#include "sim/system.hh"
50
51using namespace ArmISA;
52
53TableWalker::TableWalker(const Params *p)
48#include "sim/system.hh"
49
50using namespace ArmISA;
51
52TableWalker::TableWalker(const Params *p)
54 : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
53 : MemObject(p), port(this, params()->sys, params()->min_backoff,
54 params()->max_backoff, true),
55 tlb(NULL), currState(NULL), pending(false),
55 masterId(p->sys->getMasterId(name())),
56 doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
57{
58 sctlr = 0;
59}
60
61TableWalker::~TableWalker()
62{

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89 currState = NULL;
90 }
91}
92
93Port*
94TableWalker::getPort(const std::string &if_name, int idx)
95{
96 if (if_name == "port") {
56 masterId(p->sys->getMasterId(name())),
57 doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
58{
59 sctlr = 0;
60}
61
62TableWalker::~TableWalker()
63{

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90 currState = NULL;
91 }
92}
93
94Port*
95TableWalker::getPort(const std::string &if_name, int idx)
96{
97 if (if_name == "port") {
97 if (port != NULL)
98 return port;
99 System *sys = params()->sys;
100 Tick minb = params()->min_backoff;
101 Tick maxb = params()->max_backoff;
102 port = new DmaPort(this, sys, minb, maxb, true);
103 return port;
98 return &port;
104 }
105 return NULL;
106}
107
108Fault
109TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
110 TLB::Translation *_trans, bool _timing, bool _functional)
111{

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220 }
221
222 Request::Flags flag = 0;
223 if (currState->sctlr.c == 0) {
224 flag = Request::UNCACHEABLE;
225 }
226
227 if (currState->timing) {
99 }
100 return NULL;
101}
102
103Fault
104TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
105 TLB::Translation *_trans, bool _timing, bool _functional)
106{

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215 }
216
217 Request::Flags flag = 0;
218 if (currState->sctlr.c == 0) {
219 flag = Request::UNCACHEABLE;
220 }
221
222 if (currState->timing) {
228 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
229 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
230 currState->tc->getCpuPtr()->ticks(1), flag);
223 port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
224 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
225 currState->tc->getCpuPtr()->ticks(1), flag);
231 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
232 stateQueueL1.size());
233 stateQueueL1.push_back(currState);
234 currState = NULL;
235 } else if (!currState->functional) {
226 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
227 stateQueueL1.size());
228 stateQueueL1.push_back(currState);
229 currState = NULL;
230 } else if (!currState->functional) {
236 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
237 NULL, (uint8_t*)&currState->l1Desc.data,
238 currState->tc->getCpuPtr()->ticks(1), flag);
231 port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
232 NULL, (uint8_t*)&currState->l1Desc.data,
233 currState->tc->getCpuPtr()->ticks(1), flag);
239 doL1Descriptor();
240 f = currState->fault;
241 } else {
242 RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
243 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
244 pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
234 doL1Descriptor();
235 f = currState->fault;
236 } else {
237 RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
238 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
239 pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
245 port->sendFunctional(pkt);
240 port.sendFunctional(pkt);
246 doL1Descriptor();
247 delete req;
248 delete pkt;
249 f = currState->fault;
250 }
251
252 return f;
253}

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569 currState->req = NULL;
570 }
571 return;
572 }
573
574
575 if (currState->timing) {
576 currState->delayed = true;
241 doL1Descriptor();
242 delete req;
243 delete pkt;
244 f = currState->fault;
245 }
246
247 return f;
248}

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564 currState->req = NULL;
565 }
566 return;
567 }
568
569
570 if (currState->timing) {
571 currState->delayed = true;
577 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
572 port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
578 &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
579 currState->tc->getCpuPtr()->ticks(1));
580 } else if (!currState->functional) {
573 &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
574 currState->tc->getCpuPtr()->ticks(1));
575 } else if (!currState->functional) {
581 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
576 port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
582 NULL, (uint8_t*)&currState->l2Desc.data,
583 currState->tc->getCpuPtr()->ticks(1));
584 doL2Descriptor();
585 } else {
586 RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId);
587 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
588 pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
577 NULL, (uint8_t*)&currState->l2Desc.data,
578 currState->tc->getCpuPtr()->ticks(1));
579 doL2Descriptor();
580 } else {
581 RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId);
582 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
583 pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
589 port->sendFunctional(pkt);
584 port.sendFunctional(pkt);
590 doL2Descriptor();
591 delete req;
592 delete pkt;
593 }
594 return;
595 default:
596 panic("A new type in a 2 bit field?\n");
597 }

--- 158 unchanged lines hidden --- 		585 doL2Descriptor();
586 delete req;
587 delete pkt;
588 }
589 return;
590 default:
591 panic("A new type in a 2 bit field?\n");
592 }

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