table_walker.cc (7823:dac01f14f20f) table_walker.cc (7946:7c58c106d28d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 194 unchanged lines hidden (view full) ---

203 currState = NULL;
204 } else {
205 currState->tc = NULL;
206 currState->req = NULL;
207 }
208 return f;
209 }
210
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 194 unchanged lines hidden (view full) ---

203 currState = NULL;
204 } else {
205 currState->tc = NULL;
206 currState->req = NULL;
207 }
208 return f;
209 }
210
211 Request::Flags flag = 0;
212 if (currState->sctlr.c == 0) {
213 flag = Request::UNCACHEABLE;
214 }
215
211 if (currState->timing) {
212 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
213 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
216 if (currState->timing) {
217 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
218 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
214 currState->tc->getCpuPtr()->ticks(1));
219 currState->tc->getCpuPtr()->ticks(1), flag);
215 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
216 stateQueueL1.size());
217 stateQueueL1.push_back(currState);
218 currState = NULL;
219 } else {
220 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
221 stateQueueL1.size());
222 stateQueueL1.push_back(currState);
223 currState = NULL;
224 } else {
220 Request::Flags flag = 0;
221 if (currState->sctlr.c == 0){
222 flag = Request::UNCACHEABLE;
223 }
224 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
225 NULL, (uint8_t*)&currState->l1Desc.data,
226 currState->tc->getCpuPtr()->ticks(1), flag);
227 doL1Descriptor();
228 f = currState->fault;
229 }
230
231 return f;

--- 235 unchanged lines hidden (view full) ---

467{
468 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
469 currState->vaddr, currState->l1Desc.data);
470 TlbEntry te;
471
472 switch (currState->l1Desc.type()) {
473 case L1Descriptor::Ignore:
474 case L1Descriptor::Reserved:
225 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
226 NULL, (uint8_t*)&currState->l1Desc.data,
227 currState->tc->getCpuPtr()->ticks(1), flag);
228 doL1Descriptor();
229 f = currState->fault;
230 }
231
232 return f;

--- 235 unchanged lines hidden (view full) ---

468{
469 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
470 currState->vaddr, currState->l1Desc.data);
471 TlbEntry te;
472
473 switch (currState->l1Desc.type()) {
474 case L1Descriptor::Ignore:
475 case L1Descriptor::Reserved:
475 if (!currState->delayed) {
476 if (!currState->timing) {
476 currState->tc = NULL;
477 currState->req = NULL;
478 }
479 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
480 if (currState->isFetch)
481 currState->fault =
482 new PrefetchAbort(currState->vaddr, ArmFault::Translation0);
483 else

--- 88 unchanged lines hidden (view full) ---

572TableWalker::doL2Descriptor()
573{
574 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
575 currState->vaddr, currState->l2Desc.data);
576 TlbEntry te;
577
578 if (currState->l2Desc.invalid()) {
579 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
477 currState->tc = NULL;
478 currState->req = NULL;
479 }
480 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
481 if (currState->isFetch)
482 currState->fault =
483 new PrefetchAbort(currState->vaddr, ArmFault::Translation0);
484 else

--- 88 unchanged lines hidden (view full) ---

573TableWalker::doL2Descriptor()
574{
575 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
576 currState->vaddr, currState->l2Desc.data);
577 TlbEntry te;
578
579 if (currState->l2Desc.invalid()) {
580 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
580 if (!currState->delayed) {
581 if (!currState->timing) {
581 currState->tc = NULL;
582 currState->req = NULL;
583 }
584 if (currState->isFetch)
585 currState->fault =
586 new PrefetchAbort(currState->vaddr, ArmFault::Translation1);
587 else
588 currState->fault =

--- 28 unchanged lines hidden (view full) ---

617 te.vpn = currState->vaddr >> te.N;
618 te.global = currState->l2Desc.global();
619 te.xn = currState->l2Desc.xn();
620 te.ap = currState->l2Desc.ap();
621 te.domain = currState->l1Desc.domain();
622 memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(),
623 currState->l2Desc.shareable());
624
582 currState->tc = NULL;
583 currState->req = NULL;
584 }
585 if (currState->isFetch)
586 currState->fault =
587 new PrefetchAbort(currState->vaddr, ArmFault::Translation1);
588 else
589 currState->fault =

--- 28 unchanged lines hidden (view full) ---

618 te.vpn = currState->vaddr >> te.N;
619 te.global = currState->l2Desc.global();
620 te.xn = currState->l2Desc.xn();
621 te.ap = currState->l2Desc.ap();
622 te.domain = currState->l1Desc.domain();
623 memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(),
624 currState->l2Desc.shareable());
625
625 if (!currState->delayed) {
626 if (!currState->timing) {
626 currState->tc = NULL;
627 currState->req = NULL;
628 }
629 tlb->insert(currState->vaddr, te);
630}
631
632void
633TableWalker::doL1DescriptorWrapper()

--- 93 unchanged lines hidden --- 		627 currState->tc = NULL;
628 currState->req = NULL;
629 }
630 tlb->insert(currState->vaddr, te);
631}
632
633void
634TableWalker::doL1DescriptorWrapper()

--- 93 unchanged lines hidden ---