table_walker.cc (7694:de057cccee82) table_walker.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 93 unchanged lines hidden (view full) ---

102 currState->req = _req;
103 currState->fault = NoFault;
104 currState->contextId = _cid;
105 currState->timing = _timing;
106 currState->mode = _mode;
107
108 /** @todo These should be cached or grabbed from cached copies in
109 the TLB, all these miscreg reads are expensive */
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 93 unchanged lines hidden (view full) ---

102 currState->req = _req;
103 currState->fault = NoFault;
104 currState->contextId = _cid;
105 currState->timing = _timing;
106 currState->mode = _mode;
107
108 /** @todo These should be cached or grabbed from cached copies in
109 the TLB, all these miscreg reads are expensive */
110 currState->vaddr = currState->req->getVaddr() & ~PcModeMask;
110 currState->vaddr = currState->req->getVaddr();
111 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR);
112 sctlr = currState->sctlr;
113 currState->N = currState->tc->readMiscReg(MISCREG_TTBCR);
114
115 currState->isFetch = (currState->mode == TLB::Execute);
116 currState->isWrite = (currState->mode == TLB::Write);
117
118 Addr ttbr = 0;

--- 532 unchanged lines hidden --- 		111 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR);
112 sctlr = currState->sctlr;
113 currState->N = currState->tc->readMiscReg(MISCREG_TTBCR);
114
115 currState->isFetch = (currState->mode == TLB::Execute);
116 currState->isWrite = (currState->mode == TLB::Write);
117
118 Addr ttbr = 0;

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