table_walker.cc (7611:c119da5a80c8) table_walker.cc (7653:968302e54850)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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155 }
156 return f;
157 }
158
159 if (currState->timing) {
160 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
161 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0);
162 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 146 unchanged lines hidden (view full) ---

155 }
156 return f;
157 }
158
159 if (currState->timing) {
160 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
161 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0);
162 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
163 stateQueue.size());
164 stateQueue.push_back(currState);
165 assert(stateQueue.size() < 5);
163 stateQueueL1.size());
164 stateQueueL1.push_back(currState);
166 currState = NULL;
167 } else {
168 Request::Flags flag = 0;
169 if (currState->sctlr.c == 0){
170 flag = Request::UNCACHEABLE;
171 }
172 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
173 NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag);

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572 currState->req = NULL;
573 }
574 tlb->insert(currState->vaddr, te);
575}
576
577void
578TableWalker::doL1DescriptorWrapper()
579{
165 currState = NULL;
166 } else {
167 Request::Flags flag = 0;
168 if (currState->sctlr.c == 0){
169 flag = Request::UNCACHEABLE;
170 }
171 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
172 NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag);

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571 currState->req = NULL;
572 }
573 tlb->insert(currState->vaddr, te);
574}
575
576void
577TableWalker::doL1DescriptorWrapper()
578{
580 currState = stateQueue.front();
579 currState = stateQueueL1.front();
581 currState->delayed = false;
582
583 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
584 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
585
586 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr);
587 doL1Descriptor();
588
580 currState->delayed = false;
581
582 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
583 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
584
585 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr);
586 doL1Descriptor();
587
588 stateQueueL1.pop_front();
589 // Check if fault was generated
590 if (currState->fault != NoFault) {
591 currState->transState->finish(currState->fault, currState->req,
592 currState->tc, currState->mode);
593
594 currState->req = NULL;
595 currState->tc = NULL;
596 currState->delayed = false;
597
589 // Check if fault was generated
590 if (currState->fault != NoFault) {
591 currState->transState->finish(currState->fault, currState->req,
592 currState->tc, currState->mode);
593
594 currState->req = NULL;
595 currState->tc = NULL;
596 currState->delayed = false;
597
598 stateQueue.pop_front();
599 }
600 else if (!currState->delayed) {
598 }
599 else if (!currState->delayed) {
600 // delay is not set so there is no L2 to do
601 DPRINTF(TLBVerbose, "calling translateTiming again\n");
602 currState->fault = tlb->translateTiming(currState->req, currState->tc,
603 currState->transState, currState->mode);
604
605 currState->req = NULL;
606 currState->tc = NULL;
607 currState->delayed = false;
608
601 DPRINTF(TLBVerbose, "calling translateTiming again\n");
602 currState->fault = tlb->translateTiming(currState->req, currState->tc,
603 currState->transState, currState->mode);
604
605 currState->req = NULL;
606 currState->tc = NULL;
607 currState->delayed = false;
608
609 stateQueue.pop_front();
609 delete currState;
610 } else {
611 // need to do L2 descriptor
612 stateQueueL2.push_back(currState);
610 }
611 currState = NULL;
612}
613
614void
615TableWalker::doL2DescriptorWrapper()
616{
613 }
614 currState = NULL;
615}
616
617void
618TableWalker::doL2DescriptorWrapper()
619{
617 currState = stateQueue.front();
620 currState = stateQueueL2.front();
618 assert(currState->delayed);
619
620 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
621 currState->vaddr);
622 doL2Descriptor();
623
624 // Check if fault was generated
625 if (currState->fault != NoFault) {

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631 currState->fault = tlb->translateTiming(currState->req, currState->tc,
632 currState->transState, currState->mode);
633 }
634
635 currState->req = NULL;
636 currState->tc = NULL;
637 currState->delayed = false;
638
621 assert(currState->delayed);
622
623 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
624 currState->vaddr);
625 doL2Descriptor();
626
627 // Check if fault was generated
628 if (currState->fault != NoFault) {

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634 currState->fault = tlb->translateTiming(currState->req, currState->tc,
635 currState->transState, currState->mode);
636 }
637
638 currState->req = NULL;
639 currState->tc = NULL;
640 currState->delayed = false;
641
639 stateQueue.pop_front();
642 stateQueueL2.pop_front();
643 delete currState;
640 currState = NULL;
641}
642
643ArmISA::TableWalker *
644ArmTableWalkerParams::create()
645{
646 return new ArmISA::TableWalker(this);
647}
648
644 currState = NULL;
645}
646
647ArmISA::TableWalker *
648ArmTableWalkerParams::create()
649{
650 return new ArmISA::TableWalker(this);
651}
652