table_walker.cc (7579:06fe5d901fe8) table_walker.cc (7582:a24f26bf0fbe)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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177void
178TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
179 uint8_t texcb, bool s)
180{
181 // Note: tc and sctlr local variables are hiding tc and sctrl class
182 // variables
183 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
184 te.shareable = false; // default value
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 168 unchanged lines hidden (view full) ---

177void
178TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
179 uint8_t texcb, bool s)
180{
181 // Note: tc and sctlr local variables are hiding tc and sctrl class
182 // variables
183 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
184 te.shareable = false; // default value
185 te.nonCacheable = false;
185 bool outer_shareable = false;
186 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
187 switch(texcb) {
188 case 0: // Stongly-ordered
189 te.nonCacheable = true;
190 te.mtype = TlbEntry::StronglyOrdered;
191 te.shareable = true;
192 te.innerAttrs = 1;

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251 default:
252 panic("More than 32 states for 5 bits?\n");
253 }
254 } else {
255 assert(tc);
256 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
257 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
258 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
186 bool outer_shareable = false;
187 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
188 switch(texcb) {
189 case 0: // Stongly-ordered
190 te.nonCacheable = true;
191 te.mtype = TlbEntry::StronglyOrdered;
192 te.shareable = true;
193 te.innerAttrs = 1;

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252 default:
253 panic("More than 32 states for 5 bits?\n");
254 }
255 } else {
256 assert(tc);
257 PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
258 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
259 DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
259 uint8_t curr_tr, curr_ir, curr_or;
260 uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
260 switch(bits(texcb, 2,0)) {
261 case 0:
262 curr_tr = prrr.tr0;
263 curr_ir = nmrr.ir0;
264 curr_or = nmrr.or0;
265 outer_shareable = (prrr.nos0 == 0);
266 break;
267 case 1:

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452 te.xn = currState->l1Desc.xn();
453 te.ap = currState->l1Desc.ap();
454 te.domain = currState->l1Desc.domain();
455 te.asid = currState->contextId;
456 memAttrs(currState->tc, te, currState->sctlr,
457 currState->l1Desc.texcb(), currState->l1Desc.shareable());
458
459 DPRINTF(TLB, "Inserting Section Descriptor into TLB\n");
261 switch(bits(texcb, 2,0)) {
262 case 0:
263 curr_tr = prrr.tr0;
264 curr_ir = nmrr.ir0;
265 curr_or = nmrr.or0;
266 outer_shareable = (prrr.nos0 == 0);
267 break;
268 case 1:

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453 te.xn = currState->l1Desc.xn();
454 te.ap = currState->l1Desc.ap();
455 te.domain = currState->l1Desc.domain();
456 te.asid = currState->contextId;
457 memAttrs(currState->tc, te, currState->sctlr,
458 currState->l1Desc.texcb(), currState->l1Desc.shareable());
459
460 DPRINTF(TLB, "Inserting Section Descriptor into TLB\n");
460 DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n",
461 DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n",
461 te.N, te.pfn, te.size, te.global, te.valid);
462 te.N, te.pfn, te.size, te.global, te.valid);
462 DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n",
463 te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid);
463 DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n",
464 te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid,
465 te.nonCacheable);
464 DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n",
465 currState->l1Desc.domain(), currState->l1Desc.data,
466 (currState->l1Desc.data >> 5) & 0xF );
467
468 if (!currState->timing) {
469 currState->tc = NULL;
470 currState->req = NULL;
471 }

--- 172 unchanged lines hidden --- 		466 DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n",
467 currState->l1Desc.domain(), currState->l1Desc.data,
468 (currState->l1Desc.data >> 5) & 0xF );
469
470 if (!currState->timing) {
471 currState->tc = NULL;
472 currState->req = NULL;
473 }

--- 172 unchanged lines hidden ---