table_walker.cc (7404:bfc74724914e) table_walker.cc (7406:ddc26bd4ea7d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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106
107 isFetch = (mode == TLB::Execute);
108 isWrite = (mode == TLB::Write);
109 isPriv = (cpsr.mode != MODE_USER);
110
111 // If translation isn't enabled, we shouldn't be here
112 assert(sctlr.m);
113
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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106
107 isFetch = (mode == TLB::Execute);
108 isWrite = (mode == TLB::Write);
109 isPriv = (cpsr.mode != MODE_USER);
110
111 // If translation isn't enabled, we shouldn't be here
112 assert(sctlr.m);
113
114 if (N == 0 || mbits(vaddr, 31, 32-N)) {
114 DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n",
115 vaddr, N, mbits(vaddr, 31, 32-N));
116
117 if (N == 0 || !mbits(vaddr, 31, 32-N)) {
118 DPRINTF(TLB, " - Selecting TTBR0\n");
115 ttbr = tc->readMiscReg(MISCREG_TTBR0);
116 } else {
119 ttbr = tc->readMiscReg(MISCREG_TTBR0);
120 } else {
117 ttbr = tc->readMiscReg(MISCREG_TTBR0);
121 DPRINTF(TLB, " - Selecting TTBR1\n");
122 ttbr = tc->readMiscReg(MISCREG_TTBR1);
118 N = 0;
119 }
120
121 Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(vaddr,31-N,20) << 2);
123 N = 0;
124 }
125
126 Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(vaddr,31-N,20) << 2);
122 DPRINTF(TLB, "Begining table walk for address %#x at descriptor %#x\n",
123 vaddr, l1desc_addr);
127 DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr);
124
125
126 // Trickbox address check
127 fault = tlb->walkTrickBoxCheck(l1desc_addr, vaddr, sizeof(uint32_t),
128
129
130 // Trickbox address check
131 fault = tlb->walkTrickBoxCheck(l1desc_addr, vaddr, sizeof(uint32_t),
128 isFetch, 0, true);
132 isFetch, isWrite, 0, true);
129 if (fault) {
130 tc = NULL;
131 req = NULL;
132 return fault;
133 }
134
135 if (timing) {
136 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),

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205 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", vaddr, l1Desc.data);
206 TlbEntry te;
207
208 switch (l1Desc.type()) {
209 case L1Descriptor::Ignore:
210 case L1Descriptor::Reserved:
211 tc = NULL;
212 req = NULL;
133 if (fault) {
134 tc = NULL;
135 req = NULL;
136 return fault;
137 }
138
139 if (timing) {
140 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),

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209 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", vaddr, l1Desc.data);
210 TlbEntry te;
211
212 switch (l1Desc.type()) {
213 case L1Descriptor::Ignore:
214 case L1Descriptor::Reserved:
215 tc = NULL;
216 req = NULL;
213 fault = new DataAbort(vaddr, NULL, isWrite, ArmFault::Translation0);
217 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
218 if (isFetch)
219 fault = new PrefetchAbort(vaddr, ArmFault::Translation0);
220 else
221 fault = new DataAbort(vaddr, NULL, isWrite, ArmFault::Translation0);
214 return;
215 case L1Descriptor::Section:
216 if (sctlr.afe && bits(l1Desc.ap(), 0) == 0)
217 panic("Haven't implemented AFE\n");
218
219 if (l1Desc.supersection()) {
220 panic("Haven't implemented supersections\n");
221 }

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247 return;
248 case L1Descriptor::PageTable:
249 Addr l2desc_addr;
250 l2desc_addr = l1Desc.l2Addr() | (bits(vaddr, 19,12) << 2);
251 DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", l2desc_addr);
252
253 // Trickbox address check
254 fault = tlb->walkTrickBoxCheck(l2desc_addr, vaddr, sizeof(uint32_t),
222 return;
223 case L1Descriptor::Section:
224 if (sctlr.afe && bits(l1Desc.ap(), 0) == 0)
225 panic("Haven't implemented AFE\n");
226
227 if (l1Desc.supersection()) {
228 panic("Haven't implemented supersections\n");
229 }

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255 return;
256 case L1Descriptor::PageTable:
257 Addr l2desc_addr;
258 l2desc_addr = l1Desc.l2Addr() | (bits(vaddr, 19,12) << 2);
259 DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", l2desc_addr);
260
261 // Trickbox address check
262 fault = tlb->walkTrickBoxCheck(l2desc_addr, vaddr, sizeof(uint32_t),
255 isFetch, l1Desc.domain(), false);
263 isFetch, isWrite, l1Desc.domain(), false);
256 if (fault) {
257 tc = NULL;
258 req = NULL;
259 return;
260 }
261
262
263 if (timing) {

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282
283 if (sctlr.afe && bits(l1Desc.ap(), 0) == 0)
284 panic("Haven't implemented AFE\n");
285
286 if (l2Desc.invalid()) {
287 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
288 tc = NULL;
289 req = NULL;
264 if (fault) {
265 tc = NULL;
266 req = NULL;
267 return;
268 }
269
270
271 if (timing) {

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290
291 if (sctlr.afe && bits(l1Desc.ap(), 0) == 0)
292 panic("Haven't implemented AFE\n");
293
294 if (l2Desc.invalid()) {
295 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
296 tc = NULL;
297 req = NULL;
290 fault = new DataAbort(vaddr, l1Desc.domain(), isWrite, ArmFault::Translation1);
298 if (isFetch)
299 fault = new PrefetchAbort(vaddr, ArmFault::Translation1);
300 else
301 fault = new DataAbort(vaddr, l1Desc.domain(), isWrite, ArmFault::Translation1);
291 return;
292 }
293
294 if (l2Desc.large()) {
295 te.N = 16;
296 te.pfn = l2Desc.pfn();
297 } else {
298 te.N = 12;

--- 25 unchanged lines hidden --- 		302 return;
303 }
304
305 if (l2Desc.large()) {
306 te.N = 16;
307 te.pfn = l2Desc.pfn();
308 } else {
309 te.N = 12;

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