table_walker.cc (13018:9e9819585e55) table_walker.cc (13019:3fa5ab820fa8)
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 757 unchanged lines hidden (view full) ---

766 L2, L3, L3, __, // sl0 == 0
767 L1, L2, L2, __, // sl0 == 1, etc.
768 L0, L1, L1, __,
769 __, __, __, __
770 };
771 start_lookup_level = SLL[sl_tg];
772 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
773 "Cannot discern lookup level from vtcr.{sl0,tg0}");
1/*
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 757 unchanged lines hidden (view full) ---

766 L2, L3, L3, __, // sl0 == 0
767 L1, L2, L2, __, // sl0 == 1, etc.
768 L0, L1, L1, __,
769 __, __, __, __
770 };
771 start_lookup_level = SLL[sl_tg];
772 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
773 "Cannot discern lookup level from vtcr.{sl0,tg0}");
774 } else switch (bits(currState->vaddr, 63,48)) {
775 case 0:
776 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
777 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
778 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
779 tg = GrainMap_tg0[currState->tcr.tg0];
780 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
781 currState->tcr.epd0)
782 fault = true;
783 break;
784 case 0xffff:
785 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
786 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
787 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
788 tg = GrainMap_tg1[currState->tcr.tg1];
789 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
790 currState->tcr.epd1)
791 fault = true;
792 break;
793 default:
794 // top two bytes must be all 0s or all 1s, else invalid addr
795 fault = true;
774 ps = currState->vtcr.ps;
775 } else {
776 switch (bits(currState->vaddr, 63,48)) {
777 case 0:
778 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
779 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
780 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
781 tg = GrainMap_tg0[currState->tcr.tg0];
782 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
783 currState->tcr.epd0)
784 fault = true;
785 break;
786 case 0xffff:
787 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
788 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
789 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
790 tg = GrainMap_tg1[currState->tcr.tg1];
791 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
792 currState->tcr.epd1)
793 fault = true;
794 break;
795 default:
796 // top two bytes must be all 0s or all 1s, else invalid addr
797 fault = true;
798 }
799 ps = currState->tcr.ips;
796 }
800 }
797 ps = currState->tcr.ips;
798 break;
799 case EL2:
800 switch(bits(currState->vaddr, 63,48)) {
801 case 0:
802 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
803 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
804 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
805 tg = GrainMap_tg0[currState->tcr.tg0];

--- 1479 unchanged lines hidden --- 		801 break;
802 case EL2:
803 switch(bits(currState->vaddr, 63,48)) {
804 case 0:
805 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
806 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
807 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
808 tg = GrainMap_tg0[currState->tcr.tg0];

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