table_walker.cc (12526:94adfd8b5dbd) table_walker.cc (12709:faf5b471d5ce)
1/*
1/*
2 * Copyright (c) 2010, 2012-2017 ARM Limited
2 * Copyright (c) 2010, 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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734Fault
735TableWalker::processWalkAArch64()
736{
737 assert(currState->aarch64);
738
739 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
740 currState->vaddr_tainted, currState->tcr);
741
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 723 unchanged lines hidden (view full) ---

734Fault
735TableWalker::processWalkAArch64()
736{
737 assert(currState->aarch64);
738
739 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
740 currState->vaddr_tainted, currState->tcr);
741
742 static const GrainSize GrainMapDefault[] =
742 static const GrainSize GrainMap_tg0[] =
743 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
743 { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
744 static const GrainSize GrainMap_EL1_tg1[] =
744 static const GrainSize GrainMap_tg1[] =
745 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };
746
747 statWalkWaitTime.sample(curTick() - currState->startTime);
748
749 // Determine TTBR, table size, granule size and phys. address range
750 Addr ttbr = 0;
751 int tsz = 0, ps = 0;
752 GrainSize tg = Grain4KB; // grain size computed from tg* field
753 bool fault = false;
754
755 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
756
757 switch (currState->el) {
758 case EL0:
759 case EL1:
760 if (isStage2) {
761 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
762 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
763 tsz = 64 - currState->vtcr.t0sz64;
745 { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };
746
747 statWalkWaitTime.sample(curTick() - currState->startTime);
748
749 // Determine TTBR, table size, granule size and phys. address range
750 Addr ttbr = 0;
751 int tsz = 0, ps = 0;
752 GrainSize tg = Grain4KB; // grain size computed from tg* field
753 bool fault = false;
754
755 LookupLevel start_lookup_level = MAX_LOOKUP_LEVELS;
756
757 switch (currState->el) {
758 case EL0:
759 case EL1:
760 if (isStage2) {
761 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
762 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
763 tsz = 64 - currState->vtcr.t0sz64;
764 tg = GrainMapDefault[currState->vtcr.tg0];
764 tg = GrainMap_tg0[currState->vtcr.tg0];
765 // ARM DDI 0487A.f D7-2148
766 // The starting level of stage 2 translation depends on
767 // VTCR_EL2.SL0 and VTCR_EL2.TG0
768 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
769 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
770 static const LookupLevel SLL[] = {
771 L2, L3, L3, __, // sl0 == 0
772 L1, L2, L2, __, // sl0 == 1, etc.
773 L0, L1, L1, __,
774 __, __, __, __
775 };
776 start_lookup_level = SLL[sl_tg];
777 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
778 "Cannot discern lookup level from vtcr.{sl0,tg0}");
779 } else switch (bits(currState->vaddr, 63,48)) {
780 case 0:
781 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
782 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
783 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
765 // ARM DDI 0487A.f D7-2148
766 // The starting level of stage 2 translation depends on
767 // VTCR_EL2.SL0 and VTCR_EL2.TG0
768 LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
769 uint8_t sl_tg = (currState->vtcr.sl0 << 2) | currState->vtcr.tg0;
770 static const LookupLevel SLL[] = {
771 L2, L3, L3, __, // sl0 == 0
772 L1, L2, L2, __, // sl0 == 1, etc.
773 L0, L1, L1, __,
774 __, __, __, __
775 };
776 start_lookup_level = SLL[sl_tg];
777 panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
778 "Cannot discern lookup level from vtcr.{sl0,tg0}");
779 } else switch (bits(currState->vaddr, 63,48)) {
780 case 0:
781 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
782 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
783 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
784 tg = GrainMapDefault[currState->tcr.tg0];
784 tg = GrainMap_tg0[currState->tcr.tg0];
785 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
786 currState->tcr.epd0)
787 fault = true;
788 break;
789 case 0xffff:
790 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
791 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
792 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
785 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
786 currState->tcr.epd0)
787 fault = true;
788 break;
789 case 0xffff:
790 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
791 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
792 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
793 tg = GrainMap_EL1_tg1[currState->tcr.tg1];
793 tg = GrainMap_tg1[currState->tcr.tg1];
794 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
795 currState->tcr.epd1)
796 fault = true;
797 break;
798 default:
799 // top two bytes must be all 0s or all 1s, else invalid addr
800 fault = true;
801 }
802 ps = currState->tcr.ips;
803 break;
804 case EL2:
794 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
795 currState->tcr.epd1)
796 fault = true;
797 break;
798 default:
799 // top two bytes must be all 0s or all 1s, else invalid addr
800 fault = true;
801 }
802 ps = currState->tcr.ips;
803 break;
804 case EL2:
805 switch(bits(currState->vaddr, 63,48)) {
806 case 0:
807 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
808 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
809 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
810 tg = GrainMap_tg0[currState->tcr.tg0];
811 break;
812
813 case 0xffff:
814 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
815 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
816 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
817 tg = GrainMap_tg1[currState->tcr.tg1];
818 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
819 currState->tcr.epd1 || !currState->hcr.e2h)
820 fault = true;
821 break;
822
823 default:
824 // invalid addr if top two bytes are not all 0s
825 fault = true;
826 }
827 ps = currState->tcr.ips;
828 break;
805 case EL3:
806 switch(bits(currState->vaddr, 63,48)) {
807 case 0:
808 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
829 case EL3:
830 switch(bits(currState->vaddr, 63,48)) {
831 case 0:
832 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
809 if (currState->el == EL2)
810 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
811 else
812 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
833 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
813 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
834 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
814 tg = GrainMapDefault[currState->tcr.tg0];
835 tg = GrainMap_tg0[currState->tcr.tg0];
815 break;
816 default:
817 // invalid addr if top two bytes are not all 0s
818 fault = true;
819 }
820 ps = currState->tcr.ips;
821 break;
822 }

--- 1454 unchanged lines hidden --- 		836 break;
837 default:
838 // invalid addr if top two bytes are not all 0s
839 fault = true;
840 }
841 ps = currState->tcr.ips;
842 break;
843 }

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