1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 */ 39 40#include "arch/arm/faults.hh" 41#include "arch/arm/table_walker.hh" 42#include "arch/arm/tlb.hh" 43#include "cpu/base.hh" 44#include "cpu/thread_context.hh" 45#include "debug/Checkpoint.hh" |
46#include "debug/Drain.hh" |
47#include "debug/TLB.hh" 48#include "debug/TLBVerbose.hh" 49#include "sim/system.hh" 50 51using namespace ArmISA; 52 53TableWalker::TableWalker(const Params *p) 54 : MemObject(p), port(this, params()->sys, params()->min_backoff, |
55 params()->max_backoff), drainEvent(NULL), |
56 tlb(NULL), currState(NULL), pending(false), 57 masterId(p->sys->getMasterId(name())), 58 doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) 59{ 60 sctlr = 0; 61} 62 63TableWalker::~TableWalker() 64{ 65 ; 66} 67 |
68void 69TableWalker::completeDrain() 70{ 71 if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() && 72 pendingQueue.empty()) { 73 changeState(Drained); 74 DPRINTF(Drain, "TableWalker done draining, processing drain event\n"); 75 drainEvent->process(); 76 drainEvent = NULL; 77 } 78} 79 |
80unsigned int 81TableWalker::drain(Event *de) 82{ |
83 unsigned int count = port.drain(de); 84 85 if (stateQueueL1.empty() && stateQueueL2.empty() && 86 pendingQueue.empty()) { 87 changeState(Drained); 88 DPRINTF(Drain, "TableWalker free, no need to drain\n"); 89 90 // table walker is drained, but its ports may still need to be drained 91 return count; 92 } else { 93 drainEvent = de; |
94 changeState(Draining); |
95 DPRINTF(Drain, "TableWalker not drained\n"); 96 97 // return port drain count plus the table walker itself needs to drain 98 return count + 1; 99 |
100 } |
101} 102 103void 104TableWalker::resume() 105{ 106 MemObject::resume(); 107 if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { |
108 delete currState; 109 currState = NULL; |
110 } 111} 112 113MasterPort& 114TableWalker::getMasterPort(const std::string &if_name, int idx) 115{ 116 if (if_name == "port") { 117 return port; --- 563 unchanged lines hidden (view full) --- 681 682 DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data); 683 DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data); 684 685 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); 686 doL1Descriptor(); 687 688 stateQueueL1.pop_front(); |
689 completeDrain(); |
690 // Check if fault was generated 691 if (currState->fault != NoFault) { 692 currState->transState->finish(currState->fault, currState->req, 693 currState->tc, currState->mode); 694 695 pending = false; 696 nextWalk(currState->tc); 697 --- 40 unchanged lines hidden (view full) --- 738 else { 739 DPRINTF(TLBVerbose, "calling translateTiming again\n"); 740 currState->fault = tlb->translateTiming(currState->req, currState->tc, 741 currState->transState, currState->mode); 742 } 743 744 745 stateQueueL2.pop_front(); |
746 completeDrain(); |
747 pending = false; 748 nextWalk(currState->tc); 749 750 currState->req = NULL; 751 currState->tc = NULL; 752 currState->delayed = false; 753 754 delete currState; --- 18 unchanged lines hidden --- |