1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 93 unchanged lines hidden (view full) --- 102 port = new DmaPort(this, sys, minb, maxb, true); 103 return port; 104 } 105 return NULL; 106} 107 108Fault 109TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, |
110 TLB::Translation *_trans, bool _timing, bool _functional) |
111{ |
112 assert(!(_functional && _timing)); |
113 if (!currState) { 114 // For atomic mode, a new WalkerState instance should be only created 115 // once per TLB. For timing mode, a new instance is generated for every 116 // TLB miss. 117 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 118 119 currState = new WalkerState(); 120 currState->tableWalker = this; --- 11 unchanged lines hidden (view full) --- 132 } 133 134 currState->tc = _tc; 135 currState->transState = _trans; 136 currState->req = _req; 137 currState->fault = NoFault; 138 currState->contextId = _cid; 139 currState->timing = _timing; |
140 currState->functional = _functional; |
141 currState->mode = _mode; 142 143 /** @todo These should be cached or grabbed from cached copies in 144 the TLB, all these miscreg reads are expensive */ 145 currState->vaddr = currState->req->getVaddr(); 146 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 147 sctlr = currState->sctlr; 148 currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); --- 78 unchanged lines hidden (view full) --- 227 if (currState->timing) { 228 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 229 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, 230 currState->tc->getCpuPtr()->ticks(1), flag); 231 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 232 stateQueueL1.size()); 233 stateQueueL1.push_back(currState); 234 currState = NULL; |
235 } else if (!currState->functional) { |
236 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 237 NULL, (uint8_t*)&currState->l1Desc.data, 238 currState->tc->getCpuPtr()->ticks(1), flag); 239 doL1Descriptor(); 240 f = currState->fault; |
241 } else { 242 RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag); 243 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 244 pkt->dataStatic((uint8_t*)&currState->l1Desc.data); 245 port->sendFunctional(pkt); 246 doL1Descriptor(); 247 delete req; 248 delete pkt; 249 f = currState->fault; |
250 } 251 252 return f; 253} 254 255void 256TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 257 uint8_t texcb, bool s) --- 314 unchanged lines hidden (view full) --- 572 } 573 574 575 if (currState->timing) { 576 currState->delayed = true; 577 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 578 &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 579 currState->tc->getCpuPtr()->ticks(1)); |
580 } else if (!currState->functional) { |
581 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), 582 NULL, (uint8_t*)&currState->l2Desc.data, 583 currState->tc->getCpuPtr()->ticks(1)); 584 doL2Descriptor(); |
585 } else { 586 RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0); 587 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 588 pkt->dataStatic((uint8_t*)&currState->l2Desc.data); 589 port->sendFunctional(pkt); 590 doL2Descriptor(); 591 delete req; 592 delete pkt; |
593 } 594 return; 595 default: 596 panic("A new type in a 2 bit field?\n"); 597 } 598} 599 600void --- 155 unchanged lines hidden --- |