1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 100 unchanged lines hidden (view full) --- 109 if (!currState) { 110 // For atomic mode, a new WalkerState instance should be only created 111 // once per TLB. For timing mode, a new instance is generated for every 112 // TLB miss. 113 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); 114 115 currState = new WalkerState(); 116 currState->tableWalker = this; |
117 } else if (_timing) { 118 // This is a translation that was completed and then faulted again 119 // because some underlying parameters that affect the translation 120 // changed out from under us (e.g. asid). It will either be a 121 // misprediction, in which case nothing will happen or we'll use 122 // this fault to re-execute the faulting instruction which should clean 123 // up everything. 124 if (currState->vaddr == _req->getVaddr()) { 125 return new ReExec; 126 } |
127 panic("currState should always be empty in timing mode!\n"); 128 } 129 130 currState->tc = _tc; 131 currState->transState = _trans; 132 currState->req = _req; 133 currState->fault = NoFault; 134 currState->contextId = _cid; --- 599 unchanged lines hidden --- |