1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 194 unchanged lines hidden (view full) --- 203 currState = NULL; 204 } else { 205 currState->tc = NULL; 206 currState->req = NULL; 207 } 208 return f; 209 } 210 |
211 Request::Flags flag = 0; 212 if (currState->sctlr.c == 0) { 213 flag = Request::UNCACHEABLE; 214 } 215 |
216 if (currState->timing) { 217 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 218 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, |
219 currState->tc->getCpuPtr()->ticks(1), flag); |
220 DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", 221 stateQueueL1.size()); 222 stateQueueL1.push_back(currState); 223 currState = NULL; 224 } else { |
225 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), 226 NULL, (uint8_t*)&currState->l1Desc.data, 227 currState->tc->getCpuPtr()->ticks(1), flag); 228 doL1Descriptor(); 229 f = currState->fault; 230 } 231 232 return f; --- 235 unchanged lines hidden (view full) --- 468{ 469 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 470 currState->vaddr, currState->l1Desc.data); 471 TlbEntry te; 472 473 switch (currState->l1Desc.type()) { 474 case L1Descriptor::Ignore: 475 case L1Descriptor::Reserved: |
476 if (!currState->timing) { |
477 currState->tc = NULL; 478 currState->req = NULL; 479 } 480 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); 481 if (currState->isFetch) 482 currState->fault = 483 new PrefetchAbort(currState->vaddr, ArmFault::Translation0); 484 else --- 88 unchanged lines hidden (view full) --- 573TableWalker::doL2Descriptor() 574{ 575 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 576 currState->vaddr, currState->l2Desc.data); 577 TlbEntry te; 578 579 if (currState->l2Desc.invalid()) { 580 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); |
581 if (!currState->timing) { |
582 currState->tc = NULL; 583 currState->req = NULL; 584 } 585 if (currState->isFetch) 586 currState->fault = 587 new PrefetchAbort(currState->vaddr, ArmFault::Translation1); 588 else 589 currState->fault = --- 28 unchanged lines hidden (view full) --- 618 te.vpn = currState->vaddr >> te.N; 619 te.global = currState->l2Desc.global(); 620 te.xn = currState->l2Desc.xn(); 621 te.ap = currState->l2Desc.ap(); 622 te.domain = currState->l1Desc.domain(); 623 memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 624 currState->l2Desc.shareable()); 625 |
626 if (!currState->timing) { |
627 currState->tc = NULL; 628 currState->req = NULL; 629 } 630 tlb->insert(currState->vaddr, te); 631} 632 633void 634TableWalker::doL1DescriptorWrapper() --- 93 unchanged lines hidden --- |