1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 */ 39 40#include "arch/arm/faults.hh" 41#include "arch/arm/table_walker.hh" 42#include "arch/arm/tlb.hh" 43#include "dev/io_device.hh" 44#include "cpu/thread_context.hh" 45 |
46#define NUM_WALKERS 2 // 2 should be enough to handle crossing page boundaries |
47 48using namespace ArmISA; 49 50TableWalker::TableWalker(const Params *p) |
51 : MemObject(p), stateQueue(NUM_WALKERS), port(NULL), tlb(NULL), 52 currState(NULL), doL1DescEvent(this), doL2DescEvent(this) 53{ 54 sctlr = NULL; 55} |
56 57TableWalker::~TableWalker() 58{ 59 ; 60} 61 62 63unsigned int --- 17 unchanged lines hidden (view full) --- 81 } 82 return NULL; 83} 84 85Fault 86TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode, 87 TLB::Translation *_trans, bool _timing) 88{ |
89 if (!currState) { 90 // For atomic mode, a new WalkerState instance should be only created 91 // once per TLB. For timing mode, a new instance is generated for every 92 // TLB miss. 93 DPRINTF(TLBVerbose, "creating new instance of WalkerState\n"); |
94 |
95 currState = new WalkerState(); 96 currState->tableWalker = this; 97 } 98 else if (_timing) { 99 panic("currState should always be empty in timing mode!\n"); 100 } |
101 |
102 currState->tc = _tc; 103 currState->transState = _trans; 104 currState->req = _req; 105 currState->fault = NoFault; 106 currState->contextId = _cid; 107 currState->timing = _timing; 108 currState->mode = _mode; 109 |
110 /** @todo These should be cached or grabbed from cached copies in 111 the TLB, all these miscreg reads are expensive */ |
112 currState->vaddr = currState->req->getVaddr() & ~PcModeMask; 113 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR); 114 sctlr = currState->sctlr; 115 currState->cpsr = currState->tc->readMiscReg(MISCREG_CPSR); 116 currState->N = currState->tc->readMiscReg(MISCREG_TTBCR); |
117 |
118 currState->isFetch = (currState->mode == TLB::Execute); 119 currState->isWrite = (currState->mode == TLB::Write); 120 currState->isPriv = (currState->cpsr.mode != MODE_USER); |
121 |
122 Addr ttbr = 0; 123 |
124 // If translation isn't enabled, we shouldn't be here |
125 assert(currState->sctlr.m); |
126 127 DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n", |
128 currState->vaddr, currState->N, mbits(currState->vaddr, 31, 129 32-currState->N)); |
130 |
131 if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) { |
132 DPRINTF(TLB, " - Selecting TTBR0\n"); |
133 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0); |
134 } else { 135 DPRINTF(TLB, " - Selecting TTBR1\n"); |
136 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1); 137 currState->N = 0; |
138 } 139 |
140 Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) | 141 (bits(currState->vaddr,31-currState->N,20) << 2); |
142 DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr); 143 144 145 // Trickbox address check |
146 Fault f; 147 f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t), 148 currState->isFetch, currState->isWrite, 0, true); 149 if (f) { 150 currState->tc = NULL; 151 currState->req = NULL; 152 return f; |
153 } 154 |
155 if (currState->timing) { |
156 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), |
157 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0); 158 DPRINTF(TLBVerbose, "Adding to walker fifo: %d free before adding\n", 159 stateQueue.free_slots()); 160 stateQueue.add(*currState); 161 currState = NULL; |
162 } else { 163 port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), |
164 NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0); |
165 doL1Descriptor(); |
166 f = currState->fault; |
167 } 168 |
169 return f; |
170} 171 172void |
173TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 174 uint8_t texcb, bool s) |
175{ |
176 // Note: tc and sctlr local variables are hiding tc and sctrl class 177 // variables |
178 DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s); 179 te.shareable = false; // default value 180 bool outer_shareable = false; |
181 if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) { |
182 switch(texcb) { 183 case 0: // Stongly-ordered 184 te.nonCacheable = true; 185 te.mtype = TlbEntry::StronglyOrdered; 186 te.shareable = true; 187 te.innerAttrs = 1; 188 te.outerAttrs = 0; 189 break; --- 19 unchanged lines hidden (view full) --- 209 case 4: // Outer and Inner Non-cacheable 210 te.nonCacheable = true; 211 te.mtype = TlbEntry::Normal; 212 te.shareable = s; 213 te.innerAttrs = 0; 214 te.outerAttrs = bits(texcb, 1, 0); 215 break; 216 case 5: // Reserved |
217 panic("Reserved texcb value!\n"); |
218 break; 219 case 6: // Implementation Defined |
220 panic("Implementation-defined texcb value!\n"); |
221 break; 222 case 7: // Outer and Inner Write-Back, Write-Allocate 223 te.mtype = TlbEntry::Normal; 224 te.shareable = s; 225 te.innerAttrs = 5; 226 te.outerAttrs = 1; 227 break; 228 case 8: // Non-shareable Device 229 te.nonCacheable = true; 230 te.mtype = TlbEntry::Device; 231 te.shareable = false; 232 te.innerAttrs = 3; 233 te.outerAttrs = 0; 234 break; 235 case 9 ... 15: // Reserved |
236 panic("Reserved texcb value!\n"); |
237 break; 238 case 16 ... 31: // Cacheable Memory 239 te.mtype = TlbEntry::Normal; 240 te.shareable = s; 241 if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0) 242 te.nonCacheable = true; 243 te.innerAttrs = bits(texcb, 1, 0); 244 te.outerAttrs = bits(texcb, 3, 2); --- 78 unchanged lines hidden (view full) --- 323 case 2: 324 DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n", 325 prrr.ns1, prrr.ns0, s); 326 te.mtype = TlbEntry::Normal; 327 if (prrr.ns1 && s) 328 te.shareable = true; 329 if (prrr.ns0 && !s) 330 te.shareable = true; |
331 break; 332 case 3: 333 panic("Reserved type"); 334 } 335 336 if (te.mtype == TlbEntry::Normal){ 337 switch(curr_ir) { 338 case 0: --- 23 unchanged lines hidden (view full) --- 362 te.outerAttrs = 2; 363 break; 364 case 3: 365 te.outerAttrs = 3; 366 break; 367 } 368 } 369 } |
370 DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ 371 outerAttrs: %d\n", 372 te.shareable, te.innerAttrs, te.outerAttrs); |
373 374 /** Formatting for Physical Address Register (PAR) 375 * Only including lower bits (TLB info here) 376 * PAR: 377 * PA [31:12] 378 * Reserved [11] 379 * TLB info [10:1] 380 * NOS [10] (Not Outer Sharable) --- 16 unchanged lines hidden (view full) --- 397 ); 398 399 400} 401 402void 403TableWalker::doL1Descriptor() 404{ |
405 DPRINTF(TLB, "L1 descriptor for %#x is %#x\n", 406 currState->vaddr, currState->l1Desc.data); |
407 TlbEntry te; 408 |
409 switch (currState->l1Desc.type()) { |
410 case L1Descriptor::Ignore: 411 case L1Descriptor::Reserved: |
412 if (!currState->delayed) { 413 currState->tc = NULL; 414 currState->req = NULL; |
415 } 416 DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n"); |
417 if (currState->isFetch) 418 currState->fault = 419 new PrefetchAbort(currState->vaddr, ArmFault::Translation0); |
420 else |
421 currState->fault = 422 new DataAbort(currState->vaddr, NULL, currState->isWrite, |
423 ArmFault::Translation0); 424 return; 425 case L1Descriptor::Section: |
426 if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { |
427 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is 428 * enabled if set, do l1.Desc.setAp0() instead of generating 429 * AccessFlag0 430 */ 431 |
432 currState->fault = 433 new DataAbort(currState->vaddr, NULL, currState->isWrite, |
434 ArmFault::AccessFlag0); 435 } 436 |
437 if (currState->l1Desc.supersection()) { |
438 panic("Haven't implemented supersections\n"); 439 } 440 te.N = 20; |
441 te.pfn = currState->l1Desc.pfn(); |
442 te.size = (1<<te.N) - 1; |
443 te.global = !currState->l1Desc.global(); |
444 te.valid = true; |
445 te.vpn = currState->vaddr >> te.N; |
446 te.sNp = true; |
447 te.xn = currState->l1Desc.xn(); 448 te.ap = currState->l1Desc.ap(); 449 te.domain = currState->l1Desc.domain(); 450 te.asid = currState->contextId; 451 memAttrs(currState->tc, te, currState->sctlr, 452 currState->l1Desc.texcb(), currState->l1Desc.shareable()); |
453 454 DPRINTF(TLB, "Inserting Section Descriptor into TLB\n"); 455 DPRINTF(TLB, " - N%d pfn:%#x size: %#x global:%d valid: %d\n", 456 te.N, te.pfn, te.size, te.global, te.valid); 457 DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d\n", 458 te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid); 459 DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n", |
460 currState->l1Desc.domain(), currState->l1Desc.data, 461 (currState->l1Desc.data >> 5) & 0xF ); |
462 |
463 if (!currState->timing) { 464 currState->tc = NULL; 465 currState->req = NULL; |
466 } |
467 tlb->insert(currState->vaddr, te); |
468 469 return; 470 case L1Descriptor::PageTable: 471 Addr l2desc_addr; |
472 l2desc_addr = currState->l1Desc.l2Addr() | 473 (bits(currState->vaddr, 19,12) << 2); |
474 DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n", 475 l2desc_addr); 476 477 // Trickbox address check |
478 currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr, 479 sizeof(uint32_t), currState->isFetch, currState->isWrite, 480 currState->l1Desc.domain(), false); 481 482 if (currState->fault) { 483 if (!currState->timing) { 484 currState->tc = NULL; 485 currState->req = NULL; |
486 } 487 return; 488 } 489 490 |
491 if (currState->timing) { 492 currState->delayed = true; |
493 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), |
494 &doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 0); |
495 } else { 496 port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t), |
497 NULL, (uint8_t*)&currState->l2Desc.data, 0); |
498 doL2Descriptor(); 499 } 500 return; 501 default: 502 panic("A new type in a 2 bit field?\n"); 503 } 504} 505 506void 507TableWalker::doL2Descriptor() 508{ |
509 DPRINTF(TLB, "L2 descriptor for %#x is %#x\n", 510 currState->vaddr, currState->l2Desc.data); |
511 TlbEntry te; 512 |
513 if (currState->l2Desc.invalid()) { |
514 DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); |
515 if (!currState->delayed) { 516 currState->tc = NULL; 517 currState->req = NULL; |
518 } |
519 if (currState->isFetch) 520 currState->fault = 521 new PrefetchAbort(currState->vaddr, ArmFault::Translation1); |
522 else |
523 currState->fault = 524 new DataAbort(currState->vaddr, currState->l1Desc.domain(), 525 currState->isWrite, ArmFault::Translation1); |
526 return; 527 } 528 |
529 if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) { |
530 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled 531 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0 532 */ 533 |
534 currState->fault = 535 new DataAbort(currState->vaddr, NULL, currState->isWrite, 536 ArmFault::AccessFlag1); 537 |
538 } 539 |
540 if (currState->l2Desc.large()) { |
541 te.N = 16; |
542 te.pfn = currState->l2Desc.pfn(); |
543 } else { 544 te.N = 12; |
545 te.pfn = currState->l2Desc.pfn(); |
546 } 547 548 te.valid = true; 549 te.size = (1 << te.N) - 1; |
550 te.asid = currState->contextId; |
551 te.sNp = false; |
552 te.vpn = currState->vaddr >> te.N; 553 te.global = currState->l2Desc.global(); 554 te.xn = currState->l2Desc.xn(); 555 te.ap = currState->l2Desc.ap(); 556 te.domain = currState->l1Desc.domain(); 557 memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), 558 currState->l2Desc.shareable()); |
559 |
560 if (!currState->delayed) { 561 currState->tc = NULL; 562 currState->req = NULL; |
563 } |
564 tlb->insert(currState->vaddr, te); |
565} 566 567void 568TableWalker::doL1DescriptorWrapper() 569{ |
570 currState = stateQueue.peek(); 571 currState->delayed = false; |
572 |
573 DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr); |
574 doL1Descriptor(); 575 576 // Check if fault was generated |
577 if (currState->fault != NoFault) { 578 currState->transState->finish(currState->fault, currState->req, 579 currState->tc, currState->mode); |
580 |
581 currState->req = NULL; 582 currState->tc = NULL; 583 currState->delayed = false; 584 585 stateQueue.remove(); |
586 } |
587 else if (!currState->delayed) { |
588 DPRINTF(TLBVerbose, "calling translateTiming again\n"); |
589 currState->fault = tlb->translateTiming(currState->req, currState->tc, 590 currState->transState, currState->mode); |
591 |
592 currState->req = NULL; 593 currState->tc = NULL; 594 currState->delayed = false; 595 596 stateQueue.remove(); |
597 } |
598 currState = NULL; |
599} 600 601void 602TableWalker::doL2DescriptorWrapper() 603{ |
604 currState = stateQueue.peek(); 605 assert(currState->delayed); |
606 |
607 DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n", 608 currState->vaddr); |
609 doL2Descriptor(); 610 611 // Check if fault was generated |
612 if (currState->fault != NoFault) { 613 currState->transState->finish(currState->fault, currState->req, 614 currState->tc, currState->mode); |
615 } 616 else { 617 DPRINTF(TLBVerbose, "calling translateTiming again\n"); |
618 currState->fault = tlb->translateTiming(currState->req, currState->tc, 619 currState->transState, currState->mode); |
620 } 621 |
622 currState->req = NULL; 623 currState->tc = NULL; 624 currState->delayed = false; 625 626 stateQueue.remove(); 627 currState = NULL; |
628} 629 630ArmISA::TableWalker * 631ArmTableWalkerParams::create() 632{ 633 return new ArmISA::TableWalker(this); 634} 635 |