1/* 2 * Copyright (c) 2010, 2012-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 170 unchanged lines hidden (view full) --- 179 if (params()->sys->isTimingMode() && currState) { 180 delete currState; 181 currState = NULL; 182 pendingChange(); 183 } 184} 185 186Fault |
187TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, |
188 uint8_t _vmid, bool _isHyp, TLB::Mode _mode, 189 TLB::Translation *_trans, bool _timing, bool _functional, 190 bool secure, TLB::ArmTranslationType tranType, 191 bool _stage2Req) 192{ 193 assert(!(_functional && _timing)); 194 ++statWalks; 195 --- 1820 unchanged lines hidden (view full) --- 2016 stateQueues[queueIndex].push_back(currState); 2017 currState = NULL; 2018 } 2019 } else if (!currState->functional) { 2020 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 2021 currState->tc->getCpuPtr()->clockPeriod(), flags); 2022 (this->*doDescriptor)(); 2023 } else { |
2024 RequestPtr req = std::make_shared<Request>( 2025 descAddr, numBytes, flags, masterId); 2026 |
2027 req->taskId(ContextSwitchTaskId::DMA); 2028 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2029 pkt->dataStatic(data); 2030 port->sendFunctional(pkt); 2031 (this->*doDescriptor)(); |
2032 delete pkt; 2033 } 2034 } 2035 return (isTiming); 2036} 2037 2038void 2039TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor) --- 245 unchanged lines hidden --- |